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Topic: Hardware verification

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	Hardware specification, verification and implementation (Site not responding. Last check: 2007-11-03)
		Hardware description languages tend to be more practically oriented, giving a direct route to standard CAD tools, such as synthesis engines.
		In this case, we have a route both to formal verification using a propositional theorem prover, and to implementation on FPGA.
		I have in mind an array multiplier (which poses problems in verification), some small counter circuits (which illustrate problems with verifying sequential circuits), some graphics circuits (for example circle drawing), maybe a mini-processor.
	www.cs.chalmers.se /~ms/hw.html (422 words)

	[No title]
		The objective is to present a sophisticated introduction to the principles, techniques, and methods of formal hardware verification without alienating participants with in-depth theory and formal mathematics of the subject.
		This is then followed by a discussion of those matrix entries which are shown to be useful to the verification of hardware designs.
		Hardware Proof Goals: verifying the : ``satisfies'' relation: Is used to verify that an implementation ``satisfies'' the requirements of another implementation or specification.
	asic.union.edu /Asic98/Wrkshp/verification.html (857 words)

	EETimes.com - Jeda language simplifies hardware verification
		The Jeda Hardware Verification Language (HVL), a verification platform from Jeda Technologies Inc., was developed out of the need for better verification tools based upon real-world experiences of validating complex digital systems.
		Hardware architectural modeling is used by designers to simulate and prove their design assumptions early in the design process.
		Although verification test benches are developed with the full intent to maximize their reuse, one cannot anticipate how such code is used in the future.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=16502347 (3192 words)

	Hardware Verification (Site not responding. Last check: 2007-11-03)
		To apply the criterion to a particular design, one must additionally define (1) an abstraction function that relates the concrete and the abstract representations of the state of the microprocessor, and (2) an invariant condition that must be true of the processor state at the start of every instruction cycle.
		The basic technique used in the verification is equational simplification of expressions, augmented with familiar proof strategies such as instantiation, case-splitting, and induction.
		The method is first illustrated by applying to a simple, hypothetical microprocessor, and then used to verify a more complex design based on the microprocessor used in the Lilith Modula II machine.
	seclab.cs.sunysb.edu /~sekar/abs/hwverif.html (365 words)

	EETimes.com - SoCs require a new verification approach
		A SoC verification methodology must address many more issues than were prevalent even a couple years ago, in particular the integration of purchased and in-house intellectual property (IP) into new designs, the coupling of embedded software into the design, and the verification flow from core to system.
		System verification - an outward focused verification suite, that allows the IP core to be tested in-system, is necessary, and if one is not provided with the IP core, then it usually created and debugged by the verification team and/or the IP provider.
		The successful SoC verification methodology must be able to integrate multiple in-house or third-party IP cores, effectively migrate testing from the block to the system-level to maximally leverage testing, integrate software such as drivers and diagnostics, debug, and provide for the adoption of HDL acceleration and formal verification.
	www.eedesign.com /features/exclusive/OEG20020225S0074 (1846 words)

	TechOnLine - Design Teams Set to Embrace Next-Generation Hardware-Assisted Verification Platforms
		Functional verification is the only means of thoroughly debugging a design before silicon availability and the only way an engineering team can meet its goal.
		Hardware emulation is one way to alleviate the functional verification bottleneck because emulators, when properly designed, can execute at megahertz speeds.
		Over the years, hardware emulators have gotten a deservedly bad reputation and are perceived to be expensive technology, complex and hard to use.
	www.techonline.com /community/home/37488 (720 words)

	IBFI Schloss Dagstuhl - Dagstuhl Seminar 03451
		Deductive verification can be used during development to minimize the risk of their failure.
		Although the costs associated with verification are often considered high, verification methods have achieved considerable success and there is increasing industrial interest in applying such methods.
		Deductive verification is the application of these methods to system analysis; its scope ranges from using theorem provers to carry out full-scale system verification to more light-weight applications that are easier to automate, such as analyzing system properties using model checkers or other decision procedures.
	www.dagstuhl.de /03451 (716 words)

	Hardware Verification, Testing and Maintenance (Site not responding. Last check: 2007-11-03)
		While this and the two following sections separate hardware, software and communications into three topics, their operation is often interdependent, and the following verification, testing and maintenance procedures may need to be carried out with all three elements in combination.
		Hardware testing is usually more detailed and thorough than verification.
		Where modifications to hardware are made as a result of system maintenance or upgrades, it may be necessary to instigate further rounds of system verification and testing to ensure that standards are still met by the modified system.
	www.aceproject.org /main/english/et/ete05a.htm (619 words)

	EETimes, 07/04/97: EDA market formalized?
		But formal verification appeared to take wing at the 34th DAC, with new companies pushing their technologies, established ones staking out their territories and broad line vendors eagerly awaiting the right time to come to market.
		Now, the verification problem that formal attempts to address is much more complex, outstripping the ability--at least the timely cost-efficient ability--of simulation and emulation techniques to handle the problem alone.
		The interest among potential users and the evolution of some of the tools suggest that this technology, once viewed by some as an EDA parlor trick, is on the verge of breaking out into a viable commercial market.
	www.fool.com /EETimes/1997/EETimes970704e.htm (555 words)

	Hardware Verification using Coinductive Assertions (Site not responding. Last check: 2007-11-03)
		Coinduction is a useful strategy for proving that two sequential hardware designs have the same behavior.
		The combination of derivation-based and theorem prover-based verification is illustrated using two significant examples.
		First, a fault-tolerant clock synchronization circuit, suitable for use in critical applications, is developed using this combined approach.
	www.cs.indiana.edu /~psm/Dissertation (294 words)

	Research overview -- Formal verification and formal methods
		Murphi is a description language and automatic formal verification system for the high-level description of finite-state systems, including many protocols and distributed algorithms.
		We have used the system both as a verification tool and as a platform for studying state reduction methods.
		SVC is an automatic theorem-prover for a decidable fragment of first-order logic which excludes quantifiers, but includes equality, uninterpreted functions and constants, arrays, records, and bit-vectors, as well as propositional connectives.
	sprout.stanford.edu /dill/research.html (514 words)

	EETimes.com - Verification hardware to stage a comeback at DAC
		Verification hardware to stage a comeback at DAC
		Functional verification tools based on specialized hardware have been a hard sell, especially as workstations have fallen in price and surged in performance.
		Traditionally, hardware-assisted verification has comprised two markets: acceleration, in which specialized hardware speeds an existing gate-level simulator; and emulation, in which gate-level netlists are mapped into FPGAs or custom processors.
	www.eetimes.com /story/OEG20000530S0015 (2178 words)

	Beyond the Finite in Automatic Hardware Verification (ResearchIndex) (Site not responding. Last check: 2007-11-03)
		Abstract: We present a new approach to hardware verification based on describing circuits in Monadic Second-order Logic (M2L).
		We show how to use this logic to represent generic designs like n-bit adders, which are parameterized in space, and sequential circuits, where time is an unbounded parameter.
		A Tutorial on Using PVS for Hardware Verification - Owre, Rushby, Shankar, Srivas (1995)
	citeseer.ist.psu.edu /basin96beyond.html (589 words)

	Formal Verification Surveys
		D. Dill, "Formal Verification: Experiences and Future Prospects", slides from a presentation at POPL 1999.
		D. Dill and S. Tasiran, "Simulation meets Formal Verification", slides from a presentation at ICCAD 1999.
		D. Dill, "Alternative Approaches to Formal Verification (Symbolic Simulation)", slides from a presentation at CAV 1999.
	www.cerc.utexas.edu /~jay/fv_surveys (458 words)

	EETimes.com - Robust verification deserves an audit
		In our cover story, reflecting our April theme of "verification as the heart of design," the authors emphasize that the designer's ultimate goal-first-pass silicon success-can be accomplished only by paying careful attention to a comprehensive verification strategy.
		The combination of a robust verification process and proper audits should guarantee that the design is sound from a functional as well as a manufacturing point of view, say the authors.
		If they are to make verification the heart of design, designers need to be assured that their SoC has been verified as robust by an independent body that is qualified to put its figurative stamp on the design.
	www.eetimes.com /story/OEG20020329S0051 (732 words)

	Formal Hardware Verification By Symbolic Trajectory Evaluation - Jain (ResearchIndex) (Site not responding. Last check: 2007-11-03)
		This thesis concentrates on hardware systems that have a simple deterministic high-level specification but have implementations that exhibit highly nondeterministic behaviors.
		46 Formal Verification of a Pipelined Microprocessor (context) - Srivas, Bickford - 1990 ACM DBLP
		22 The Formal Verification of a Pipelined Double-Precision IEEE..
	citeseer.ist.psu.edu /jain97formal.html (1354 words)

	Hardware Verification Methodology (Site not responding. Last check: 2007-11-03)
		The previously proposed witness string method generates traces for system verification using a model checker and then uses the traces to drive the RTL logic design simulation.
		This paper extends the depth first search (DFS) used in the original witness string method with a state pruning method that exploits multiple search heuristics in simultaneous searches where each DFS uses a different heuristic.
		The state pruning method proposed in this study is motivated from the problems in digital system design and then extended to general verification.
	www.ece.umn.edu /users/wildfire/verification.html (278 words)

	Verification moves to the enterprise level: News from Cadence Design Systems
		In addition to the Incisive Enterprise family, which is tailored for multispecialist SoC and system-development teams, Cadence offers the Incisive Design Team family, with verification solutions tailored for RTL development teams, and the Incisive HDL family, for HDL creation and simulation.
		The Incisive Enterprise family is part of a new set of Cadence offerings that integrates advanced 'VPA-enabled' technologies and methodologies from the Verisity acquisition with system modelling, HDL and assertion languages, high-performance formal and dynamic engines, verification IP and analysis tailored for each specialist.
		Incisive Enterprise targets the exponentially increasing complexity of the verification process associated with the integration of multiple specialists spanning block, chip and system-level verification of SoCs and hardware-software systems.
	www.electronicstalk.com /news/cad/cad325.html (421 words)

	Hardware verification - a reference guide from Electronicstalk
		We see from your search that you're looking for information on the term "Hardware verification", and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest.
		Start with the news release Software verifies processor-based board designs from SDC Systems, which we summarised at the time by saying "Kozio is a US company that delivers a complete diagnostics and functional test platform that efficiently accelerates the development of new processor based board designs.".
		In April 2004, we covered the news from Carbon Design Systems concerning its DesignPlayer - take a look at Package accelerates verification regression which says: "New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain.".
	www.electronicstalk.com /guides/hardware-verification.html (253 words)

	RESEARCHERS IN TEST, VERIFICATION, VALIDATION, MANUFACTURABILITY AND RELATED AREAS.
		University of Cincinnati's Formal Hardware Verification ProjectTechniques for Large Scale Hardware Verification.
		Hardware Verification using Monadic Second-Order LogicHardware Verification using Monadic Second-Order Logic.
		Bibliography on Hardware Verification and Formal MethodsBibliography on Hardware Verification and Formal Methods.
	www.ee.pdx.edu /~mperkows/IC_LAB/test-people.html (1409 words)

	Database of Case Studies Achieved Using CADP
		The design of complex systems requires both software and hardware components, some of them being specifically designed for the application and others being reused (microprocessors, real-time kernels, etc.).
		Concretely, the authors have connected the codesign environment COSMOS and the verification environment CADP by providing transformations from the SOLAR models used for codesign and the (E-)LOTOS specifications used for verification.
		The integration of toolsets from both hardware design and formal verification areas is a promising way towards a complete environment for building complex hardware/software systems.
	www.inrialpes.fr /vasy/cadp/case-studies/99-h-codesign.html (376 words)

	Effective Theorem Proving for Hardware Verification
		The attractiveness of using theorem provers for system design verification lies in their generality.
		The major practical challenge confronting theorem proving technology is in combining this generality with an acceptable degree of automation.
		We describe an approach for enhancing the effectiveness of theorem provers for hardware verification through the use of efficient automatic procedures for rewriting, arithmetic and equality reasoning, and an off-the-shelf BDD-based propositional simplifier.
	www.csl.sri.com /papers/tpcd94 (217 words)

	RuleBase Parallel Edition \| Homepage (Site not responding. Last check: 2007-11-03)
		RuleBase is an industrial-strength formal verification (FV) tool, developed by the IBM Haifa Research Laboratory.
		The new offering, based on breakthrough technology that was previously only available to IBM engineers, provides superior verification performance and increases the size of designs that can be formally verified.
		RuleBase PE is based on parallel, formal, and semi-formal verification algorithms that were developed in IBM Research Labs at Haifa.
	www.haifa.il.ibm.com /projects/verification/RB_Homepage/index.html (165 words)

	EETimes.com - Hardware verification platform handles 12M gates
		In the meantime, the company's new configuration should be attractive to mainstream groups that need a way to speed the verification of designs with about 12 million gates but that are unable to afford large emulation systems, Rizzatti said.
		Engineers tend to shy away from hardware verification platforms because of the partitioning chore involved, Rizzatti said.
		The systems had tens or hundreds of programmable devices that required a design be chopped into tens or hundreds of pieces to program the hardware verification system.
	www.eetimes.com /story/OEG20030428S0051 (806 words)

	Specification and Verification II
		Specification and Verification II Among the areas that Rhines highlighted as future areas of cost reduction was verification, which he said has become a major bottleneck, accounting for as much of half of a designer's time.
		But most verification being done today is redundant, Rhines said, adding that the emergence of assertion-based design would dramatically improve verification quality and reduce effort.
		Intel has developed a strong formal verification tradition with a large, experienced FV team that has applied FV methods on several previous projects, most notably the Pentium 4 in Oregon.
	www.cl.cam.ac.uk /users/mjcg/Teaching/SpecVer2/SpecVer2.html (1052 words)

	Hardware Research History (Site not responding. Last check: 2007-11-03)
		Computational Logic performed a broad range of research in hardware verification using the Nqthm and ACL2 logics as specification and proving tools.
		VHDL, the VHSIC Hardware Description Language, is an event driven simulation language that permits netlist level and behavioral level descriptions of hardware designs.
		We formally specified the machine-level interface of the CAP as an aid in the architectural definition of the device, as well as providing a basis for verifying its internal hardware and the software that runs on it.
	www.computationallogic.com /hardware (283 words)

	IBM Research \| Projects \| Hardware Verification
		Simulation and formal methods are vital and complementary components of IBM's hardware design process.
		IBM Research has a long history of innovation in hardware verification that includes high performance hardware simulation engines as well as Boolean equivalence checking and advanced model checking.
		For a comprehensive view of the verification program in IBM Research see: http://www.research.ibm.com/pics/verification/.
	www.research.ibm.com /da/verification.html (82 words)

	Amazon.com: Introduction to Formal Hardware Verification: Books: Thomas Kropf (Site not responding. Last check: 2007-11-03)
		Hardware verification is a hot topic in circuit and system design due to rising circuit complexity.
		This advanced textbook presents an almost complete overview of techniques for hardware verification.
		It covers all approaches used in existing tools, such as binary and word-level decision diagrams, symbolic methods for equivalence checking, and temporal logic model checking, and introduces the use of higher-order logic theorem proving for verifying circuit correctness.
	www.amazon.com /exec/obidos/tg/detail/-/3540654453?v=glance (703 words)

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