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	Advanced packaging solution
		In turn, IC package designers are under intense pressure to keep pace.
		At the same time, packaging technology itself is undergoing rapid change, including the move to multi-layer flip-chip packaging to accommodate 1000+ I/O pins and multiple stacked die systems-in-package (SiP) designs, which often provide a viable alternative to SoC implementations.
		The unique Cadence approach to advanced IC packaging breaks through the accepted ad hoc system of isolated job tasks and expert engineering.
	www.cadence.com /solutions/advanced_packaging/index.aspx?lid=advanced_packaging (447 words)

	The Chip Collection - IC Packaging 1982 Series 9 - Smithsonian Institution
		Packages may be simple or they maybe complex-depending on the nature of the device, the system of which it is a part and the environment in which the device must operate.
		The cerdip package (see Figure 3) is a sandwich structure with a ceramic base and lid bonded (with glass frit) to surround the leadframe assembly on which the chip is mounted.
		Earlier this year, ICE completed a significant multiclient study entitled, "Electronic Packaging Strategies for the 80s." In this study we indicated that leaded chip carriers were the preferred technology and that leadless versions would be relegated to a niche market, serving high-rel and military applications where a ceramic substrate was required or desirable.
	smithsonianchips.si.edu /ice/package.htm (2105 words)

	IC Packaging and Test Roadmaps (Site not responding. Last check: 2007-10-14)
		IC packaging has become a critical link between wafer processing and electrical testing both in technology and manufacturing food chain.
		While some IC packaging technologies are becoming commodity-like, IC packaging professionals are facing challenges in technical as well as non-technical areas along with the demands on multi-role and multi-function.
		Assembly and packaging innovation is essential and it is underway at an unprecedented rate.
	www.meptec.org /06IC_Packaging.html (2195 words)

	Electronic Packaging
		Since the primary concerns of the packaging industry at that time were purely in regard to the mechanical aspects of the packages, with virtually no attention given to the electrical issues (with the possible exception of DC lead resistance), many of the packages simply could not perform well at higher frequencies.
		To address the high frequency AC packaging issues, in 1979 the Mayo group began the design of a family of custom leadless chip carriers (Figure EP-2), with serious attention given to their high frequency behavior.
		The Mayo group has undertaken the task of packaging these components in such a way that they can be connected together on a substrate which in turn supports the delivery of DC power to the chips, and also supports the testing of the components, both individually and in a connected chain.
	www.mayo.edu /sppdg/packaging_development.html (2693 words)

	MOSIS Packaging Options
		The package specified should have the same cavity size as the actual package to be used for assembly.
		The lines on the diagram representing the bonding wires, drawn from bonding pads on the die to the center of the package bonding fingers, are the same width as the bonding pads (approximately 100 micrometers or 4 mils).
		If you are interested in plastic packages, send a message to support@mosis.com, specifying the package parameters (package type, lead count, body size, and pad size of interest).
	www.mosis.org /Technical/Packaging/pkg-intro.html (2822 words)

	My-ESM - Integration ignites IC packaging trends (Site not responding. Last check: 2007-10-14)
		The higher margins typically associated with newer packages are expected to drive up revenue for SATS providers 10% to 17% this year, according to analysts' estimates, with most of the growth coming in the second half of this year.
		Packaging is becoming more complicated, particularly for cell phones, which need flash memory and logic chips in a single package, according to Ramsay.
		Packaging costs are also climbing because they have to meet new silicon requirements for fine pitch, finer bond pads, thinner form factors, and a whole new set of cost and performance characteristics associated with the electronics industry's drive toward lead-free components.
	www.my-esm.com /showArticle.jhtml?articleID=6511982 (1934 words)

	Advanced Packaging
		In our history of packaging RandD innovation, TI was among the first to develop software models for the mechanical, thermal and electrical characteristics of packages.
		This information allows us to develop packages that provide the full performance entitlement of the silicon to our customers, reduce soft errors related to packaging, and last for the life of the system.
		Other packaging innovations and areas we are working on include the introduction of quad flat no-head packages (QFNs), wafer-scale packaging, the development of low-stress polymer compounds, and the adaptation of more resilient materials to withstand drop tests and other types of mechanical and handling punishment inflicted on mobile systems.
	www.ti.com /research/docs/advancedpackaging.shtml (423 words)

	ELECTRONIC DESIGN - June 8, 1998 - Collective Design Advances IC Packaging (Site not responding. Last check: 2007-10-14)
		In enhanced plastic packages, I/O counts may be higher to avoid adding extra layers, thus in-package capacitance is generally not feasible.
		The flex circuit is attached to the surface of an IC using a semiconductor-grade elastometer; its structure forms the basic redistribution layer or interposer.
		Some of this catch-up relates to the package itself, and some is related to the manner in which the I/Os of the chip were designed.
	www.elecdesign.com /Globals/PlanetEE/Content/2055.html (2835 words)

	Outsourced IC packaging to reach $13.1B
		The market scale of outsourced IC packaging is estimated to reach $13.1 billion this year, with Taiwan gradually emerging as a powerhouse in the industry segment, according to a Research and Markets report.
		However, Japan often performs well in the IC substrate field, so tight business relationship between Taiwan and Japan is formed as Japanese companies transfer their technologies to Taiwan when there is inadequacy in production capacity.
		Packaging accounts for five to 25 percent of the total cost of a complete semiconductor product, and such proportion may increase as technology advances.
	www.eetasia.com /ART_8800441505_480300_e692d19d200611.HTM (528 words)

	IC Packaging
		We are committed to providing high quality, quick turnaround semiconductor assembly and packaging services to our neighbors in Silicon Valley and customers throughout the United States and Worldwide.
		PROMEX provides a variety of integrated circuit assembly and packaging capabilities to become a vital business partner to its' customers.
		A wide range of standard plastic package assembly services for mid-size lots as well as prototype and engineering lots is offered.
	www.promex-ind.com /packaging/index.htm (120 words)

	EETimes.com - Philips slams IC-packaging, ATE sectors
		He was mainly referring to the merchant IC-assembly industry, which is plagued by the lack of standard packages.
		And not to be outdone, strong IC demand in the consumer-electronics sector will likely cause continued high prices and supply constraints in the high-end, chip-packaging markets, according to industry executives and analysts.
		IC rankings: Advanced Micro Devices and Hynix will finally break into the list of the world's top 10 semiconductor suppliers this year, according to a preliminary ranking from market research analyst iSuppli, which increased its chip industry growth forecast to 9 percent for 2006.
	www.eetimes.com /news/semi/showArticle.jhtml?articleID=189401356 (923 words)

	Actel: Products & Services: Technology Solutions: Packaging
		In order to enable next generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility.
		Actel consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance.
		Actel IC packaging technology efficiently supports high density FPGAs with large pin count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP).
	www.actel.com /products/rescenter/package (192 words)

	IC Packaging Technology - CDS’s IC PACKAGING SOFTWARE, USED BY MANY OF THE WORLDS LARGEST SILICON AND PACKAGING ...
		The IC Packaging Design Technology is part of our Master Foundry Suite.
		Get IC Packaging and other IC Packaging related tools when you purchase this suite.
		CDS's IC Packaging Software, Used by Many of the Worlds Largest Silicon and Packaging Companies, Supports all Package Types including Laminate BGA, Flex BGA, Chip Scale BGA, Enhanced or Cavity BGA, Wafer Scale BGA, etc.
	www.cad-design.com /software/icpackaging_design_technology.html (413 words)

	Cadence Releases IC Packaging Tool - SPECCTRAQuest from Cadence Design Systems - Brief Article - Product Announcement ... (Site not responding. Last check: 2007-10-14)
		SPECCTRAQuest interconnect designer for IC packaging, part of the Cadence Advanced packaging ensemble expert system, merges electrical and physical design into an environment that provides a complete solution for optimizing IC package performance.
		The result is a unified flow that enables IC package engineers to make critical design decisions much earlier in the design process.
		SPECCTRAQuest for IC packaging will be available in the third quarter, on Windows NT and Unix-based platforms, as part of the Cadence Advanced Packaging Ensemble suite, which is priced at $110,000.
	www.findarticles.com /p/articles/mi_m0EKF/is_34_45/ai_55871177 (242 words)

	CarbonLeaf, UltraCushion & CopperLeaf Wafer Separators & Cushions: IC Containers
		CarbonLeaf, UltraCushion and CopperLeaf wafer separators and cushions: IC container packaging.
		WEC Technology manufactures leading edge products that are used in the storage and transportation of IC wafers.
		The Wafer Environmental Control (WEC) packaging technology is a patent concept that provides a complete system including the environment to protect the sensitive and valuable IC wafer against the harmful effects associated with AMC.
	www.wectechnology.com (141 words)

	Intel® Packaging Information
		The Intel® Packaging Databook is intended to serve only as a data reference guide to Intel package selection and availability.
		Package characteristics and data for electrical, mechanical, and thermal IC package characteristics.
		A profile of the Tape Carrier Package and its uses in areas that require lightweight small footprint integrated circuits.
	developer.intel.com /design/packtech/packbook.htm (545 words)

	ISI Interconnect Systems Application Specific Organic IC Packaging (Site not responding. Last check: 2007-10-14)
		ISI specializes in application specific organic semiconductor packages with pin counts from 8 to 1,000+.
		ISI has designed over 150 packages for applications ranging from high performance, moderate volume to low cost, high volume.
		ISI Pin Grid Array (PGA) packages are ideal for die with low temperature ceilings.
	www.isipkg.com /packages.htm (194 words)

	Semiconductor packaging: JEDEC, package types, pitch, height, package designator, documentation
		Semiconductor packaging: JEDEC, package types, pitch, height, package designator, documentation
		At Texas Instruments, there is a wide variety of packaging being used in the manufacturing of its integrated circuits.
		This site is intended to serve as a guide to help you, the customer, understand the many aspects of packaging and its components.
	focus.ti.com /general/docs/packaging.jsp (52 words)

	IC Packaging Market Topped $23B in 2005 - Circuits Assembly
		San Jose -- With 116 billion ICs produced in 2005, the value of the worldwide IC packaging market was $23.1 billion in 2005, reports Electronic Trend Publications.
		Of this worldwide total, 37 billion ICs were assembled by contract packaging companies for a value of $9 billion.
		At that time, the value of the IC packaging market will be $34.6 billion.
	circuitsassembly.com /cms/cms/content/view/3170/95 (389 words)

	Intro to IC Packaging and Assembly - Trends and Options
		This course provides an overview of IC packaging and assembly, the current trends and the available options highlighting technical issues and reliability concerns wherever applicable.
		It focuses on packaging trends, namely the Ball Grid Array, (BGA) and the Chip Scale Package (CSP), and alternative formats, Multichip Modules (MCM), Chip On Board (COB) and 3-D initiatives at both the chip and package levels.
		This course is designed to serve as an introduction, a review, and an update of IC packaging trends and assembly options.
	www.pti-inc.com /Courses/icpackageassembly.html (438 words)

	IEEE/CPMT Tutorial: Advanced IC Packaging
		The line between the IC package and the printed circuit was once very sharp and well defined.
		Attendees will better understand not only what packaging choices and options are available, but also how they are built, their strengths and their weaknesses.
		Tutorial topics will include: IC packaging origins and options, assembly processes, flip chip and wire bonding, chip scale and wafer-level packaging, stacked technologies,test and reliability issues, the impact of lead-free requirements on IC package assembly, new and evolving IC packaging concepts.
	www.cpmt.org /scv/courses/icpkg.html (593 words)

	IC Packaging solutions for microelectronic devices, IC, JEDEC and bare die trays
		IC Packaging solutions for microelectronic devices, IC, JEDEC and bare die trays
		Entegris handling solutions assure the integrity of your valuable microelectronic devices from the front end fab, during assembly, test and 'pack' operations, and through consumption at the EMS provider.
		JEDEC matrix trays and accessories to meet your specific IC Packaging needs, both shipping and handling
	www.devicecare.com (151 words)

	Packaging Design
		Semitracks, Inc. has assembled a course on IC Packaging Design and Modeling which provides an overview of the packaging design process.
		Discussions and examples will concentrate on thermal performance simulations, assembly and packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package.
		He began work in the Central Packaging Group, Texas Instruments, Dallas in 1983 as a Group Member of the Technical Staff performing semiconductor package development, design, testing, and simulation.
	www.semitracks.com /courses/packaging-design-course.htm (342 words)

	IC package information for adapters
		Click the IC to learn about the critical dimensions used for specifying adapters.
		The type of adapter required depends on the package that you have and your application.
		ICs such as QFP also go by CQFP, TQFP, MQFP look the the package that is closest to what you are working with.
	www.adapters.com /Packages/index.html (90 words)

	IC Packaging Trends
		For most new IC products, packaging is an integral part of the chip design and production process; it is no longer just a simple, final step in the chip supply chain.
		This section provides an IC unit shipment forecast by package type (e.g., SO, FP/CC, BGA, wafer-level, bare die, etc.) and data showing how packages are evolving from simple cookie-cutter type packages to highly sophisticated and customized solutions.
		A comprehensive IC industry study that combines historical data with a five-year forecast to provide clear insight into trends within global and regional markets, product categories, and technology shifts.
	www.electronics.ca /reports/ic/icin302_15.html (231 words)

	ENGnetBASE: Engineering Handbooks Online
		The Electronic Packaging Handbook, a new volume in the Electrical Engineering Handbook Series, provides essential factual information on the design, manufacturing, and testing of electronic devices and systems.
		Electronics packaging continues to include expanding and evolving topics and technologies, as the demands for smaller, faster, and lighter products continues without signs of abatement.
		These demands mean that individuals in each of the specialty areas involved in electronics packaging-such as electronic, mechanical, and thermal designers, and manufacturing and test engineers-are all interdependent on each others knowledge.
	www.engnetbase.com /ejournals/books/book_summary/summary.asp?id=412 (200 words)

	Integrated circuit packaging - Wikipedia, the free encyclopedia
		Integrated circuit packaging is the final stage of semiconductor device fabrication per se, followed by IC testing.
		In the integrated circuit industry it is called simply packaging and sometimes semiconductor device assembly, or simply assembly.
		Also, sometimes it is called encapsulation or seal, by the name of its last step.
	en.wikipedia.org /wiki/Integrated_circuit_packaging (111 words)

	Pericom - Products - Packaging - Main Page
		The speed letter code mark is placed after the package code letter, rather than after the device number as it is ordered.
		Note:Many smaller packages are not marked with the Pericom logo due to space limitations on the package.
		View our wide range of advanced IC packaging solutions to fit any application.
	www.pericom.com /products/packaging (215 words)

	Ansoft Corporation - Q3D Extractor - What's Your Focus? - IC packaging
		Accurately characterize the performance of bond wires, signal paths, ground planes or pin/solder-ball terminations of an IC package.
		With dramatic increases in pin counts, combined with ever-smaller IC package footprints, the signal path plays a critical role in determining the dielectric performance of the device.
		It accurately characterizes the performance of the package, whether focusing on the bond wire, signal path, ground planes or pin/solder-ball terminations.
	www.ansoft.com /products/si/q3d_extractor/focus_ic.cfm (210 words)

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