IO APIC - Factbites

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Topic: IO APIC

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	IO-APIC - Wikipedia, the free encyclopedia
		The I/O Advanced Programmable Interrupt Controller (IO-APIC) is an APIC architecture originally designed by Intel for use in Symmetric Multi-Processor (SMP) computer systems.
		Uniprocessor kernels with APIC enabled can cause spurious interrupts to be generated.
		Care should be taken not to confused the APIC with the Advanced Configuration and Power Interface (APIC).
	en.wikipedia.org /wiki/IO-APIC (388 words)

	Bona Fide OSDev - Multiprocessing Support for Hobby OSes Explained
		Multiple IO APICs each have their own address range in which they are mapped, but are, again, mapped globally and accessable from all processors.
		The local APIC module is the means by which the local processor can send interrupts to the other processors and is memory mapped into the address space of the processor at the addresses in the previous table.
		However, for an IO APIC, it is mapped into the address space of all processors at the same address so that all processors can address the same IO APIC through the same address range.
	www.osdever.net /tutorials/mp.php?the_id=59 (5073 words)

	apicsubsystem.txt
		It is envisioned that a scheme for boot-time modification of the APIC ISR functions may be used as oppossed to the MACRO model used in vector.s.
		The IO APIC is then programmed to expect an external device (ExtInt in MP spec terminology) on that pin.
		When an INTerrupt is received via this channel the IO APIC does the IntAck dance with the 8259 to fetch the vector.
	people.freebsd.org /~fsmp/SMP/papers/apicsubsystem.txt (1555 words)

	NOVELL: Interrupts in the Symmetric Multi-Processing Environment.
		The purpose of the IO APIC is to receive an interrupt from one of the many devices in the system and present the interrupt to all local APICs in the system.
		However, because the IO APIC scans its input lines for active interrupts in order starting from line 0, the overall priority scheme based on the vector is not strictly enforced.
		In the APIC priority is based on the vector associated with the interrupt not the input line.
	developer.novell.com /devres/langrp/lan/dispatch/smpmemo.htm (3800 words)

	LearnThis.Info Encyclopedia articles beginning with 'Io'
		I > Io Listed below are all articles that begin with Io.
	encyclopedia.learnthis.info /i/io/index.html (26 words)

	IRQs, SATA, and APICs in the 865/875 chipset
		Basically I want to understand the relationship between IRQs, SATA, and APICs, on mainboards that use the Intel 865/875 chipset.
		Basically I want to understand the relationship = between IRQs, SATA, and APICs, on mainboards that use the Intel 865/875 = chipset.
		But the FOLDOC definition of an APIC = (http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?query=apic&action=Search) = says that it "usually has more available interrupt lines that a typical = PIC." = = - Can any of you report success or problems with throughput of SATA drives, = using the 865/875 chipset, especially in Linux?
	www.computer-one.org /new-2244498-4568.html (1095 words)

	Encyclopedia: Linux kernel
		IO-APIC (I/O Advanced Programmable Interrupt Controller) is an Intel architecture for dealing with interrupts in multi-processor computer systems.
		Improvements to the "overall responsiveness" for interactive processes (the kernel became fully preemptible and the I/O scheduler was rewritten).
		Support for futexes, a rewrite of threading infrastructure to allow the Native POSIX Thread Library (NPTL) to be used.
	www.nationmaster.com /encyclopedia/Linux-kernel (8553 words)

	LWN: Patch: Updated MSI Patches
		If the PCI device supports MSI and conforms to the +specification and the platform supports the APIC local bus, +then using MSI should work.
		In P3 IPI's are transmitted on the APIC local +bus and in P4 and Xeon they are transmitted on the system +bus.
		MSI support enables a PCI device sending an inbound +memory write (0xfeexxxxx as target address) on its PCI bus +directly to the FSB.
	lwn.net /Articles/51779 (3001 words)

	Java Hosting : io_apic : PHP JSP JAVA WebSite Web Page Web Host
		* Some Intel chipsets with IO APIC VERSION of 0x1?
		* Some Intel chipsets with IO APIC VERSION of 0x2?
		We ack the APIC in the end-IRQ handler, not
	www.oxxus.net /source/unix/source-io_apic.htm (2255 words)

	$20 sent to whoever gives me the fix this problem (seriously). - nV News Forums
		I turned off apic in the BIOS, compiled the kernel without support for apic, and sent the kernel the paramter noapic.
		I don't claim this will help "you", but might be worth a try just cause I been down this road and was no fun, was determined to get APIC or ACPI working but in the end it was out of my hands as I not a linux kernel programmer but a tweaker instead.
		Again, if I turn APIC off, the system runs super fast, but unfortunately will lock in in about two to three minutes.
	www.nvnews.net /vbulletin/showthread.php?s=&threadid=16264 (1403 words)

	discuss@linmodems.org: 9197: Re: Multiprocessor machine solved!!!?
		therefore i would assume that if the kernel > allows this boot option and actually switches off apic it will deactivate > the second cpu.
		not sure but i'd verify if both cpus are really active > and not only recognized when you run without apic.
		are you sure both cpus are still working with apic switched off?
	www.crynwr.com /cgi-bin/ezmlm-cgi/8/9197 (136 words)

	smp-2.3.18-H3
		APIC TDCR: %08x\n", v); + printk("\n"); +} + +void print_all_local_APICs (void) +{ + smp_call_function(print_local_APIC, NULL, 1, 1); + print_local_APIC(NULL); +} + static void __init init_sym_mode(void) { + struct IO_APIC_reg_01 reg_01; int i; for (i = 0; i
		+ * We _must_ ack these because every local APIC has only N + * irq slots per priority level, and a 'hanging, unacked' IRQ + * holds up an irq slot - in excessive cases (when multiple + * unexpected vectors occur) that might lock up the APIC + * completely.
		APIC ESR1: %08lx\n", v); + + ack_APIC_irq(); + + irq_err_count++; + + spin_unlock(&err_lock); +} + +/* * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts * per second.
	people.redhat.com /mingo/smp-generic-patches/smp-2.3.18-H3 (4716 words)

	Advanced Programmable Interrupt Controller
		The IO APIC is typically located at physical address FEC00000, but may be moved by programming the north/southbridge chipset.
		What the IO APIC Is This is a separate chip that is wired to the Local APIC's so it can forward interrupts on to the CPU chips.
		What the Local APIC Is As stated above, the Local APIC (LAPIC) is a circuit that is part of the CPU chip.
	osdev.berlios.de /pic.html (3407 words)

	LKML: "Andre M. Hedrick": Fix or Flaw ?? WAS (Possible cause of "spurious APIC interrupt")
		"spurious APIC interrupt, ayiee, should never happen." Should we not change the logical destination mask from all CPUs to Local.
	lkml.org /lkml/1998/5/24/9 (359 words)

	nForce3 (Compaq R3000) timer fix
		Be careful with spelling; this is 'apic', not 'acpi' this time.
	lists.freebsd.org /pipermail/freebsd-amd64/2005-January/003376.html (245 words)

	Re: grub 0.90 prevents Standby in Windows
		If you see anything other than: No local APIC present or hardware disabled Then take a look at your kernel configuration.
		A lot of uniprocessor machines support APIC and IO-APIC operation now, hence the UP (UniProcessor) configuration parameters in the Linux kernel.
		A simpler thing entirely is to run "dmesg" and grep the output for "APIC".
	www.mail-archive.com /bug-grub@gnu.org/msg04436.html (506 words)

	Netgear MA311 with Nforce2 with IO-APIC IRQ problem
		I'm about to start digging into the Intersil Prism2.5 documentation, but I thought I'd check on the list first in case anyone knows what the problem might be.
		2) The wavelan card works fine in windows XP (and I know APIC is setup the same way as it is by my patches).
		I think this is not a motherboard problem: 1) A realtek 8139-based ethernet card works fine in the same PCI slot.
	lists.shmoo.com /pipermail/hostap/2003-July/003638.html (245 words)

	Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) Datasheet
		The 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors.
		To increase system flexibility when assigning memory space usage, the I/O APIC's two-register memory space is re-locatable.
		An indirect register accessing scheme optimizes the memory space needed to access the I/O APIC's internal registers.
	www.intel.com /design/chipsets/datashts/290566.htm (131 words)

	rbed-linux-2.4.20.patch.gcc3.3-fixed
		+ * If there is no local APIC found, the processor might not + * be a P6, or the option wasn't correctly activated in the kernel.
		+ * Needed because the APIC timer is based on the bus freq + * and we want to set it with a TSC value which is based on + * the processor freq.
		/ if (unlikely(!c)) { struct task_struct p; - + spin_unlock_irq(&runqueue_lock); read_lock(&tasklist_lock); for_each_task(p) @@ -624,6 +1427,112 @@ spin_lock_irq(&runqueue_lock); goto repeat_schedule; } + + //here, because apic timer is not ready, we skip the RBED scheduling algorithm + goto normal_done; + + +RBED: +#ifdef RBED_DEBUG + rdtsc(low,high); + edf_start_tsc = ((u64)high
	www.people.virginia.edu /~rjt3k/config/rbed-linux-2.4.20.patch.gcc3.3-fixed (3581 words)

	JustLinux Forums - Apic
		What is APIC and how does it make hardware work better/more efficiently etc.?
		Ok so why is it some distros require you to add this as a boot option, while others do not?
	www.justlinux.com /forum/printthread.php?t=142000 (112 words)

	LangaList Std Edition 2002-09-26
		Some APICs provide support for reasonably exotic applications such as multiprocessing (more than one CPU in a system); but virtually all current PCs have some kind of APIC chipset built-in.
		But for the most part, PIC and APIC are terms you can just tuck away in the back of your mind--- you'll probably never have to deal with them directly.
		The core idea behind both is simply to provide a way around an ancient limitation of the classic "AT" style PC architecture, which IBM developed in 1983 or so.
	www.langa.com /newsletters/2002/2002-09-26.htm (3217 words)

	APIC problems with nforce2
		Jun 9 22:20:21 FarSite kernel: I/O APIC #2 Version 17 at 0xFEC00000.
		I've done some googling, and found that there has long been problems with the ACPI and APIC support in the linux kernel, but as I've understood, they fixed it in kernel 2.6.3.
		I have to log in to the computer from ssh/etc and kill the Xfree86 process (which is using 99% of the CPU).
	www.nforcershq.com /forum/viewtopic.php?p=381375 (825 words)

	cvs commit: src/sys/i386/acpica madt.c src/sys/i386/i386 io_apic.c local_apic.c mptable.c src/sys/i386/include apicvar.h
		jhb 2004/05/04 13:39:24 PDT FreeBSD src repository Modified files: sys/i386/acpica madt.c sys/i386/i386 io_apic.c local_apic.c mptable.c sys/i386/include apicvar.h Log: - Change the APIC code to mostly use the recently added intr_trigger and intr_polarity enums for passing around interrupt trigger modes and polarity rather than using the magic numbers 0 for level/low and 1 for edge/high.
	lists.freebsd.org /pipermail/cvs-src/2004-May/023221.html (351 words)

	Linux Kernel Patch to enable IO-APIC on some Acer laptops
		One of the more nasty bugs is, that the MADT (Multiple APIC Description Table) claims the presence of two IO-APICs, although only one is actually present.
		The Linux kernel presently panics when noticing this condition, which will usually leave you without any indication of the real problem, as the console has generally not been initialized at this stage.
		If you are interested in (and have trouble) running Linux on one of these machines, you might be interested in the fixed DSDTs.
	www.fs.tum.de /~aderesch?N=D (166 words)

	[linux-audio-user] APIC is bad?
		Florin Andrei wrote: > Well, the thing is, without APIC (default with Fedora single-CPU > kernels) there was some overlap in the way the devices were assigned > interrupts.
		Nothing bad (especially since the EMU10K1 got it's own IRQ), > but still i thought there is room for improvement.
	music.columbia.edu /pipermail/linux-audio-user/2004-July/013864.html (354 words)

	Unexpected DVD access and IO errors - SuSE Linux Forums
		And I scroll any window (say netscape), either the via the mouse wheel, scroll bars or keyboard, the IO to the DVD fails, and a small lockup seems to occur.
		flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse pni syscall mmxext 3dnowext 3dnow
		Unexpected DVD access and IO errors, SuSE 9.2 + SuSE 9.3
	forums.suselinuxsupport.de /index.php?showtopic=16135 (382 words)

	ICH2-APIC-1.diff
		: IO APIC version: %04X\n", reg_01.version); if ((reg_01.version != 0x01) && /* 82489DX IO-APICs / + (reg_01.version != 0x02) && / 82801BA IO-APICs (ICH2) / (reg_01.version != 0x10) && / oldest IO-APICs / (reg_01.version != 0x11) && / Pentium/Pro IO-APICs / (reg_01.version != 0x13) && / Xeon IO-APICs */
	www.codemonkey.org.uk /projects/patches/old/ICH2-APIC-1.diff (74 words)

	Gmane -- Mail To News And Back Again
		Setting 4 in the phys_id_present_map...changing IO-APIC physical APIC ID to 4...
		Setting 3 in the phys_id_present_map...changing IO-APIC physical APIC ID to 3...
		OEM ID: Product ID: SE7500CW2 APIC at: 0xFEE00000 I/O APIC #2 Version 32 at 0xFEC00000.
	article.gmane.org /gmane.linux.smp/1130 (379 words)

	intr.patch
		io_intsrc.is_pic = (struct pic )io; intpin->io_intpin = i; - intpin->io_vector = intbase + i; + intpin->io_irq = intbase + i; / * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
		Note + * that after we have booted ioapic_assign_cluster() + * will program the interrupt pin again, but it doesn't + * hurt to do that and trying to avoid that adds needless + * complication.
		Local APICs manage interrupts on each * individual processor as opposed to I/O APICs which receive interrupts @@ -123,6 +135,9 @@ IDTVEC(apic_isr7), /* 224 - 255 / }; +/ Include IDT_SYSCALL to make indexing easier.
	people.freebsd.org /~jhb/patches/intr.patch (3081 words)

	Education - Information - Educational Resources - Encyclopedia - Music - Io
		INDEX OF ARTICLES: Io Articles are indexed by the first word of the title, including "A," "The," etc.
		Education - Information - Educational Resources - Encyclopedia - Music - Io Shopping Stores
	education.music.us /Io.htm (248 words)

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