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Topic: Instruction level parallelism

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Tandem Computers

Vaughan Pratt

Vinod Khosla

	An Analysis of Computer Architectures For Exploiting Parallelism
		The basic idea of issuing several instructions per clock cycle is to exploit the instruction level parallelism available in the code and thus improve the performance.
		Instruction scheduling attacks several important segments of wasted bandwidth, but this is far from bringing the superscalar up to acceptable utilization.
		It takes instructions from the first thread until it comes across a branch instruction or the end of cache line and the rest are filled in from the second thread to make a total of eight.
	longwood.cs.ucf.edu /~feuerbac/papers/archpara.html (5476 words)

	Nitesh Batra Project
		ILP processors achieve their high performance by causing multiple operations to execute in parallel using a combination of compiler and hardware techniques.
		For example, the group (word) might contain four instructions, and the compiler ensures that those four instructions are not dependent on each other so they can be executed simultaneously.
		Instruction level parallelism occurs when a component of an algorithm can be executed independent of the results of another component of the algorithm.
	www.wam.umd.edu /~nbatra/411proj/vliwopening.htm (640 words)

	Instruction Level Parallelism (Site not responding. Last check: 2007-10-09)
		Freeze/Flush It is a branch handling technique in which all the instructions after a branch are either held or deleted until the branch is resolved.
		Say ideally, a machine takes one cycle to complete an instruction, if a 5 stage pipeline is used, a 2nd, 3rd, 4th instructions can be loaded parallely when the 1st instruction progresses, thus increasing the thoughput 5 times.
		Scoreboard Is a technique used to schedule instruction in a CPU dynamically, i.e using a pipeline.
	homepages.wmich.edu /~v2navane/parallel.html (695 words)

	IA-64 (Site not responding. Last check: 2007-10-09)
		In a mainstream "out-of-order" design, a complex decoder system examines each instruction as they flow through the pipeline and sees which can be fed off to operate in parallel across the available execution units — e.g.
		The ability to extract instruction level parallelism (ILP) from the instruction stream is essential to good performance in a modern CPU.
		However, since the Itanium is built primarily for speed of its EPIC-style instructions, and because it has no out-of-order execution capabilities, IA-32 code executes at a severe performance penalty compared to either the IA-64 mode, or its Pentium line of processors.
	www.brainyencyclopedia.com /encyclopedia/i/ia/ia_64.html (1082 words)

	Exploiting SuperWord Level Parallelism with Multimedia Instruction Sets
		Vector parallelism offers some respite for this problem but it can be complex and fragile and does not work for non-vectorizable loops.
		ILP is the lowest level of parallelism that involves execution of multiple instructions in parallel and requires special hardware for this purpose.
		Concepts such as loop level and vector parallelism have also been introduced that differ only on the granularity at which parallelism is extracted.
	filebox.vt.edu /a/adatey/research/SuperWord.htm (520 words)

	[No title] (Site not responding. Last check: 2007-10-09)
		In the quest for increased perfor- mance, industry and academia have been focusing more on ILP, and new tech- niques are being developed to extract higher levels of parallelism with ILP compilers and architectures.
		Instruction level parallelism has become an intense area of research.
		The goals of this conference are to bring together researchers in fields related to instruction level parallelism, to encourage interaction, and to further the state of the art in microarchitectures and fine grain parallel processing.
	american.cs.ucdavis.edu /Micro28/cfp.ascii (212 words)

	Instruction Level Parallelism
		The amount of parallelism available within a basic block (a straight-line code sequence with no branches in and out except for entry and exit) is quite small.
		Since the instructions are likely to depend upon one another, the amount of overlap we can exploit within a basic block is likely to be much less than 7.
		A loop is parallel unless there is a cycle in the dependecies, since the absence of a cycle means that the dependencies give a partial ordering on the statements.
	www.cs.iastate.edu /~prabhu/Tutorial/PIPELINE/instrLevParal.html (338 words)

	Register Pressure in Instruction Level Parallelism (Site not responding. Last check: 2007-10-09)
		This is because the continuous increasing of the gap between instruction level parallelism (ILP) processor speed and memory access latency.
		After RS and RF analysis steps, ILP scheduler is free from register constraints and final allocator may not require avoidable spilling.
		Instruction Level Parallelism, Register Allocation, Register Saturation, Register Requirement, Register Sufficiency, Software Pipelining, Integer Linear Programming, Code Optimization, Optimizing Compilation.
	www.prism.uvsq.fr /~touati/thesis.html (395 words)

	Western Research Laboratory - Compaq (Site not responding. Last check: 2007-10-09)
		Such an examination is complicated by the wide variety of hardware and software techniques for increasing the parallelism that can be expoited, including branch prediction, register renaming, and alias analysis.
		By performing simulations based on instruction traces, we can model techniques at the limits of feasibility and even beyond.
		Our study shows a striking difference between assuming that the techniques we use are perfect and merely assuming that they are impossibly good.
	www.research.compaq.com /wrl/techreports/abstracts/TN-15.html (108 words)

	ELE 658 Instruction Level Parallelism (Site not responding. Last check: 2007-10-09)
		However, little parallelism can be extracted if no attention is paid to the branches (control flow) of a program.
		Going way beyond such performance levels is the subject of our work; our latest research indicates that speedup factors in the 10's may be possible over sequentially operated machines; such speedups have been demonstrated in our initial simulations.
		This course will survey the literature in the areas of instruction level parallelism and branch effect reduction.
	www.ele.uri.edu /Courses/ele658 (223 words)

	Euro-Par 2002 - Parallel Computer Architecture and Instruction Level Parallelism (Site not responding. Last check: 2007-10-09)
		Thread-level parallelism will be harnessed in next generation of high-performance microprocessors.
		The scope of this topic will include (but is not limited to) parallel computer architectures, processor architecture (architecture and microarchitecture as well as compilation), the impact of emerging microprocessor architectures on parallel computer architectures, innovative memory designs to hide and reduce the access latency, multi-threading, and impact of emerging applications on parallel computer architecture design.
		Papers are being sought on all aspects of parallel computer architecture, processor architecture and microarchitecture, including (but not limited to) the following list of topics.
	europar.upb.de /topics/topic08.html (140 words)

	Available Technologies - Office of Technology Management (Site not responding. Last check: 2007-10-09)
		The IMPACT C-compiler incorporates instruction-level parallelism, generates C code for highly parallel applications with twice the efficiency of existing compilers, and is an open-source product.
		Hardware parallelism (i.e., execution of a large number of instructions concurrently) is increasing, which demands parallelism techniques that are not available in existing commercial compilers.
		It incorporates instruction-level parallelism and generates C code for highly parallel applications with twice the efficiency of existing compilers -- the level of efficiency that is/will be required by current and future microprocessors, specifically 64-bit microprocessors.
	www.otm.uiuc.edu /techs/techdetail.asp?id=4 (548 words)

	Computer Architecture
		Instructions with the same name but no data flow (second instruction is a write)
		Instruction Status: Which of the four steps the instruction is in
		Commit: When an instruction (other then an incorrectly predicted branch) is at the top of the buffer, update state.
	engr.smu.edu /~diaz/5381.fall98/notes/chapter04.html (1687 words)

	TechWeb - Hot Chips Trailblazes a Path to Parallelism
		The pursuit of parallelism appears to have replaced the quest for wider superscalar chips and higher clock speeds as the road to application performance.
		There can be more opportunities to dispatch operations in parallel, these architects claim, if one looks at the sub-operations-the adds, shifts, loads and so on-that make up a basic machine instruction.
		If a program is organized into multiple independent threads-sequences of instructions that do not exchange data with one another during execution-then a CPU could theoretically keep several threads loaded into its decode buffer.
	www.lightner.net /lightner/bruce/eet_hc97.html (1444 words)

	[No title]
		These two principles together allow us to execute instructions in a different order and still maintain the program semantics.
		This is the foundation upon which ILP processors are built.¡(9 tºª ó"¨Dynamic scheduling¨lConsider the example: div.d f0,f2,f4 add.d f10,f0,f8 sub.d f12,f8,f14 Where are the data dependences?
		The pipeline may have not yet completed some instructions that are earlier in program order than the instruction causing the exception.
	www.cs.mtu.edu /~soner/courses/cs4431/Lecture06.ppt (180 words)

	IBM Research \| Technical Paper Search \| Scalable instruction-level parallelism through tree-instructions
		parallelism achievable with this approach degrades less than 10% with respect
		This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication.
		Questions about this service can be mailed to reports@us.ibm.com.
	domino.research.ibm.com /library/cyberdig.nsf/a3807c5b4823c53f85256561006324be/62bc5f0df9d56a5d8525659300718f30?OpenDocument (225 words)

	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines - Jouppi, Wall (ResearchIndex)
		Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit.
		In this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism.
		A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism for a series of benchmarks.
	citeseer.ist.psu.edu /jouppi89available.html (481 words)

	"Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading" (Site not responding. Last check: 2007-10-09)
		Unfortunately, both parallel- processing styles statically partition processor resources, thus preventing them from adapting to dynamically-changing levels of TLP and ILP in a program.
		The most compelling reason for running parallel applications on an SMT processor is its ability to use thread-level parallelism and instruction- level parallelism interchangeably.
		The ease of adding additional thread contexts on an SMT (relative to adding additional processors on an MP) allows simultaneous multithreading to expose more parallelism, further increasing functional unit utilization and attaining a 52% average speedup (versus a four- processor, single-chip multiprocessor with comparable execution resources).
	www.cs.washington.edu /research/smt/papers/tlpabstract.html (467 words)

	Limits of Instruction-Level Parallelism - Wall (ResearchIndex) (Site not responding. Last check: 2007-10-09)
		Such an examination is complicated by the wide variety of hardware and software techniques for increasing the parallelism that can be exploited, including branch prediction, register renaming, and alias analysis.
		By performing simulations based on instruction traces, we can model techniques at the limits of...
		10 Detection and parallel execution of parallel instructions (context) - Tjaden, Flynn - 1970
	citeseer.ist.psu.edu /wall90limits.html (397 words)

	[No title]
		This is the best place to get info on MPI from, including implementations and the MPI forum itself.
		Using MPI: Portable Parallel Programming with the Message-Passing Interface by W. Gropp, E. Lusk, and A. Skjellum
		Parallel Computing Works, by G. Fox, R. Williams, and P. Messina (Morgan Kaufmann Publishers)
	www.cs.utk.edu /~dongarra/WEB-PAGES/cs594-2002.html (810 words)

	Encyclopedia: Instruction level parallelism
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		Updated 278 days 22 hours 22 minutes ago.
		Click for other authoritative sources for this topic (summarised at Factbites.com).
	www.nationmaster.com /encyclopedia/Instruction-level-parallelism (304 words)

	An architecture for high instruction level parallelism (Site not responding. Last check: 2007-10-09)
		High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced.
		Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently.
		The dataflow problems are reduced by increasing the number of functional units, registers, condition bits, by pipelining the functional units, and using nonblocking caches.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/hicss/1995/6930/00/6930toc.xml&DOI=10.1109/HICSS.1995.375398 (232 words)

	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture (Site not responding. Last check: 2007-10-09)
		Toward more advanced usage of instruction level parallelism by a very large data path processor architecture
		The architectural performance gain of a microprocessor is going to saturate because of the small gain of instruction level parallelism.
		This architecture broadens the window of instruction analysis to extract 10 times of parallel gain compared with the conventional superscaler processors.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/ispan/1997/8259/00/8259toc.xml&DOI=10.1109/ISPAN.1997.645134 (224 words)

	CS 352 HW1: Superscalar Pipelines and Instruction Level Parallelism
		Superscalar architecture is a method of parallel computing used in many RISC processors.
		In a superscalar computer, the central processing unit (CPU) manages multiple instruction pipelines to execute several instructions concurrently during a clock cycle.
		To successfully implement a superscalar architecture, the CPU's instruction fetching mechanism must intelligently retrieve and delegate instructions.
	paintballnewbies.com /maria/cs352 (234 words)

	Instruction Level Parallelism (Site not responding. Last check: 2007-10-09)
		Most ILP is implicit, i.e., instructions that can be
		level, in this processors the compiler codes parallel
		But applications are still written in standard sequential
	www.cs.ualberta.ca /~amaral/talks/MACI-Apr2002/sld062.htm (25 words)

	ILP - Instruction-Level Parallelism
		Its the ability of a CPU to execute multiple instructions in parallel at any one time.
		An independent living plan for the provision of IL services mutually agreed upon by an appropriate staff member of the service provider and an individual with significant disabilities.
		Every attempt has been made to provide you with the correct acronym for ILP.
	www.auditmypc.com /acronym/ILP.asp (184 words)

	Instruction-Level Parallelism - Compare Prices & Reviews at Smarter
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		Introduction to Parallel and Vector Solution of Linear Systems
		Scheduling and Load Balancing in Parallel and Distributed Systems/Eh0417-6
	www.smarter.com /books-1/product/instruction-level_parallelism-864304 (261 words)

	Comp.compilers: The Journal of Instruction-Level Parallelism Call for Papers
		The Journal of Instruction-Level Parallelism Call for Papers
		The Journal of Instruction-Level Parallelism Call for Papers beaty@emess.mscd.edu (Steve Beaty) (1999-02-27)
		The Journal of Instruction-Level Parallelism (JILP) is a Web-first,
	compilers.iecc.com /comparch/article/99-02-132 (177 words)

	Chapter 4 Exploiting Instruction-Level Parallelism with Software Approaches (Site not responding. Last check: 2007-10-09)
		John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, third edition, Morgan Kaufmann, New York, 2003.
		Advanced Compiler Support for Exposing and Exploiting ILP
		Another View: ILP in the Embedded and Mobile Markets
	www.eng.mu.edu /corlissg/173.04F/ch4.html (72 words)

	[No title] (Site not responding. Last check: 2007-10-09)
		ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP)
		ACM Symposium on Parallel Algorithms and Architectures (SPAA)
		International Symposium on Parallel Architectures and Compilation Techniques (PACT)
	cmc.rice.edu /docs/search.aspx (504 words)

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