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Topic: Instruction pipelining

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	Instruction Pipelining
		Pipelining is most suited for tasks in which essentially the same sequence of steps must be repeated many times for different data.
		Instructions which have passed this point are allowed to complete, while instructions that have not reached this point are canceled.
		Pipelines for arithmetic processing often are extended to two-dimensional structures in which input data comes from several other stages and output may be passed to more than one destination.
	www.csee.wvu.edu /~jdm/classes/cs455/notes/tech/instrpipe.html (1735 words)

	Kids.Net.Au - Encyclopedia > Instruction pipelining
		Instruction pipelining is a method for increasing the throughput of a digital circuit, particularly a CPU, and implements a form of instruction level parallelism.
		When the data finishes the first stage, the clock ticks, and the intermediate results are latched into registers at the head of the next stage, while the next set of data enters the beginning of the first stage.
		Realisticly, the time taken by the extra logic added (in the form of latches or registers) to store the intermediate values results in diminishing returns, and this extra logic also means an increase in size and cost.
	www.kids.net.au /encyclopedia-wiki/in/Instruction_pipelining (286 words)

	LinuxHPC.org/Cluster Builder 1.2 - CPU
		Often the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned.
		Instruction level parallelism (ILP) seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the utilization of on-die execution resources), and thread level parallelism (TLP) purposes to increase the number of threads (effectively individual programs) that a CPU can execute simultaneously.
		Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict.
	www.clusterbuilder.org /pages/encyclopedia/alphabetized/c/cpu.php (2417 words)

	What is pipelining? - a definition from Whatis.com
		With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed.
		Pipelining is sometimes compared to a manufacturing assembly line in which different parts of a product are being assembled at the same time although ultimately there may be some parts that have to be assembled before others are.
		The instruction pipeline represents the stages in which an instruction is moved through the processor, including its being fetched, perhaps buffered, and then executed.
	searchsmb.techtarget.com /sDefinition/0,,sid44_gci212792,00.html (407 words)

	Spartanburg SC \| GoUpstate.com \| Spartanburg Herald-Journal
		An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time).
		If 4 instructions that do not depend on the output of the first instruction are not available, the pipeline control logic must insert a stall or wasted clock cycle into the pipeline until the dependency is resolved.
		In the extreme case, the performance of a pipelined processor could theoretically approach that of an unpipelined processor, or even slightly worse if all but one pipeline stages are idle and a small overhead is present between stages.
	www.goupstate.com /apps/pbcs.dll/section?category=NEWS&template=wiki&text=instruction_pipelining (1561 words)

	Data processing apparatus and method employing instruction pipelining - Patent 4750112
		Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction.
		The pipeline control unit has circuitry for initiating operation of at least one stage of the execution pipeline using at least one of the address data formed by the instruction pipeline for program instruction prior to the completion of address data formation by the instruction pipeline for that program instruction.
		The thirty two bits of instruction data are passed on buses 62,63 to the opcode latches and selectors 80,81 on the IPP 8; this data is retained on the IPP 8 by clock pulse CID1.
	www.freepatentsonline.com /4750112.html (16208 words)

	[No title]
		In computers, a pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction.
		There are two types of pipelines, Instructional pipeline where different stages of an instruction fetch and execution are handled in a pipeline and Arithmetic pipeline where different stages of an arithmetic operation are handled along the stages of a pipeline.
		The second problem when a branch instruction comes along, it is impossible to know in advance of execution which path the program is going to take and, if the machine guesses wrong, all the partially processed instructions in the pipeline are useless and must be replaced.
	www.laynetworks.com /Pipelining.htm (1214 words)

	Pipelining
		A particular instruction might need data in a register which has not yet been stored since that is the job of a preceeding instruction which has not yet reached that step in the pipeline.
		Branch instructions are those that tell the processor to make a decision about what the next instruction to be executed should be based on the results of another instruction.
		A dynamic pipeline is divided into three units: the instruction fetch and decode unit, five to ten execute or functional units, and a commit unit.
	cse.stanford.edu /class/sophomore-college/projects-00/risc/pipelining (1479 words)

	Computer related glossary defines hardware and software terms.
		Although computers usually provide instructions that can test and manipulate bits, they generally are designed to store data and execute instructions in bit multiples called bytes.
		Pipelining In computers, a pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction.
		Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory, and so forth.
	www.cheap-computers-guide.com /computer-related-glossary.html (2267 words)

	Lecture 3: Pipelining and Instruction-Level Parallelism
		Even though the latency of a single task pushed through the entire pipeline may become worse due to overhead, the throughput of the system is increased because the pipeline stages are overlapping, i.e.
		This happens when an instruction in the pipeline depends on data from another instruction that is also in the pipeline.
		This is where data needed by one instruction is produced by a previous instruction, or where data needed by one instruction flows through a chain of dependent instructions from some source.
	camino.rutgers.edu /cs505/lecture3.html (2109 words)

	Chip Design Magazine
		Pipelining decreases combinational delays by inserting registers in long combinational paths, thereby allowing the system's clock frequency to be increased, which results in higher overall performance.
		Thus, the concept of pipelining is that, by splitting the combinational logic into smaller pieces and adding more register stages, we can increase the maximum frequency at which the circuit can operate and thereby increase the total circuit throughput in terms of the number of calculations that can be performed each second.
		During an instruction fetch, the address is supposed to be held stable by the PC register.
	www.chipdesignmag.com /print.php?articleId=245?issueId=0 (2640 words)

	p (Site not responding. Last check: )
		Pipelining is a technique that exploits parallelism among the instructions in a sequential instruction stream.
		Completing the N-i instructions that were loaded into the pipeline prior to the offending instruction takes N-i clock cycles, which are executed (a) prior to, or (b) concurrently with, the reloading of the instructions i-1 that followed the i-th instruction (in the EX stage).
		Depending on the method by which the pipeline evaluates the branch and fetches (or pre-fetches) the branch target, a maximum of two cycles penalty (one cycle for flushing, one cycle for fetching and inserting the branch target) is incurred for insertion of a stall in the case of a branch prediction error.
	www.nvc.cs.vt.edu /~cegyhazy/cs4014/Chapter8.html (7514 words)

	Central processing unit Summary
		Instructions gathered from input interfaces are executed at the CPU, and the results delivered to output interfaces.
		There are also instruction cycles, an instruction cycle being the complete round of events necessary to execute a single instruction at the machine-language level (e.g., instruction fetch, instruction decode, operand fetch, write result, etc.).
		ISAs that use variable length instruction words, such as x86, increment the PC by the number of memory words corresponding to the last instruction's length.
	www.bookrags.com /Central_processing_unit (9293 words)

	Pipelining Explained - Short-Media.com
		The word "pipelining" with respect to a processor may be a familiar word to enthusiasts but many may not know much beyond the term or even what it means.
		In the most basic terms pipelining is the ability of the processor to "cue" data it may require while the processor is completing an instruction.
		Pipelining is accomplished by adding registers in between the stages to hold the results of each individual stage.
	www.short-media.com /articles/pipelining_explained (977 words)

	Pipelining: An Overview (Part II): Page 1
		This speedup is possible because the more pipeline stages there are in a processor, the more instructions the processor can work on simultaneously and the more instructions it can complete in a given period of time.
		By breaking the processor's four-stage pipeline down into a longer series of shorter, more specialized stages, we can put even more of the processor's specialized hardware to work simultaneously on more instructions and thereby increase the number of instructions that the pipeline completes each nanosecond.
		Because pipelining requires that each pipeline stage take exactly one clock cycle to complete, then our clock cycle can now be shortened to 0.5ns in order to fit the lengths of the eight pipeline stages.
	arstechnica.com /paedia/p/pipelining-2/pipelining-2-1.html (1309 words)

	Pipelining: An Overview (Part I): Page 1
		Intel's strategy of deepening the Pentium 4's pipeline, a practice that Intel calls "hyperpipelining", has paid off in terms of performance, but it is not without its drawbacks.
		If the instruction is not a branch instruction but an arithmetic instruction, send it to the proper ALU.
		An instruction starts out in the fetch phase, moves to the decode phase, then to the execute phase, and finally to the write phase.
	arstechnica.com /paedia/p/pipelining-1/pipelining-1-1.html (731 words)

	Promise Pipelining
		CapTP's pipelining descends directly from this work, although the abstraction it pipelines is more similar to the Udanax Promise than the Joule Channel.
		And of course, if you buy the analogy, the rich CPU architecture literature on instruction pipelining with register renaming is all possibly relevant.
		And since inter-machine pipes are much deeper than instruction pipes, we potentially have a lot more to gain from (approximately) their techniques than they do.
	www.erights.org /elib/distrib/pipeline.html (952 words)

	Compaq Fortran
		Software pipelining applies instruction scheduling to certain innermost loops, allowing instructions within a loop to "wrap around" and execute in a different iteration of the loop.
		The software pipelining optimization applies instruction scheduling to certain innermost loops, allowing instructions within a loop to "wrap around" and execute in a different iteration of the loop.
		By modifying the unrolled loop and inserting instructions as needed before and/or after the unrolled loop, software pipelining generally improves run-time performance, except where the loops contain a large number of instructions with many existing overlapped operations.
	www.helsinki.fi /atk/unix/dec_manuals/cf95au54/dfuum018.htm (2576 words)

	Computer Architecture Tutorial
		This tutorial introduces undergraduate students to computer architecture concepts of caches and pipelining.
		It contains examples, interactive applets and some problems with solutions to illustrate basic ideas.
		Feedback consisting of comments and errors are welcome, and can be e-mailed to Gurpur Prabhu at prabhu@cs.iastate.edu.
	www.cs.iastate.edu /~prabhu/Tutorial/title.html (148 words)

	Using Graphics and Animation to Visualize Instruction Pipelining and its Hazards (ResearchIndex) (Site not responding. Last check: )
		Using Graphics and Animation to Visualize Instruction Pipelining and its Hazards
		Abstract: The breakthrough of pipelined microprocessors has brought about a need to teach instruction pipelining in electrical and computer engineering curricula at the undergraduate level to a considerable depth.
		Although the idea of pipelining is conceptually simple, students often find pipelining difficult to visualize.
	citeseer.ist.psu.edu /437765.html (286 words)

	ProfilerPimp
		A typical CPU processes program instructions in four basic stages, for instance: grab an instruction from memory, decode it to find out what must be done, process the instruction, then store the results.
		The concept was named pipelining, and it can make a significant difference, although there are some complications.
		Guess incorrectly and the pipeline must be flushed, throwing away its recent work altogether.
	www.profilerpimp.com (2460 words)

	What is pipelining? - A Word Definition From the Webopedia Computer Dictionary (Site not responding. Last check: )
		That is, several instructions are in the pipeline simultaneously, each at a different processing stage.
		This creates a two-stage pipeline, where data is read from or written to SRAM in one stage, and data is read from or written to memory in the other stage.
		DRAM pipelining is usually combined with another performance technique called burst mode.
	www.webopedia.com /TERM/P/pipelining.html (299 words)

	Assembly Language programming (Site not responding. Last check: )
		Instruction pre-fetching is a technique which fills the processors internal instruction queue whilst it is busy decoding/executing the current instruction.
		In fact, several register type instructions could all be executed by different DEU at the same time, resulting in certain instructions having an execution time of zero clocks.
		Instructions are executed according the fetch, decode, execute cycle.
	goforit.unk.edu /asm/p386_1.htm (2679 words)

	RISC vs. CISC Still Matters
		The instructions in the so-called CISC ISAs tend to vary considerably in length and be tightly and sequentially encoded (i.e.
		the instruction decoder had to look in one field to tell if a second optional field or extension was present, which in turn would dictate where a third field might be located in the instruction stream, and so on).
		To illustrate the large contrast between the instruction encoding formats used by CISC and RISC processors, the instruction formats for the Intel x86 and Compaq Alpha processor architectures are shown in Figure 1.
	ctas.poly.asu.edu /bgannod/CET520/Spring02/Projects/demone.htm (3537 words)

	[No title]
		The idea behind this is, that a new instruction can enter the pipeline, when the first instruction enters stage two etc..
		This way many instructions are being executed at the same time in various stages, so that no part of the CPU is idle.
		With the knowledge about the pipeline we can use a very simple trick to speed up the c2p process - we simply use the time, which is needed for the chipram writes to perform the c2p conversion.
	membres.lycos.fr /amycoders/sources/writepipe.html (671 words)

	LANai 3.0 Instruction Set - Pipeline Operation
		instruction were followed by a Register-Immediate (RI) and then a Register-Register (RR) instruction, the pipelining of the execution of this instruction context could be depicted as follows:
		The meaning of instructions is tied to the pipeline, and, in the remainder of this document, the instructions are defined operationally, in terms of the pipeline.
		If this same register were a source in the Register-Immediate instruction, the source register contents for the RI instruction would be those after time 3, i.e., before the result of the memory read is placed into this register.
	www.myri.com /scs/L3/doc/inst_2.html (297 words)

	December 93 - MAKING THE LEAP TO POWERPC
		Once an instruction is fetched and passed to the decode stage, the next instruction can be fetched without waiting for the first instruction to complete.
		When instructions are not pipelined, they complete serially, with two instructions completing in eight cycles.
		The branch processor initiates instruction execution by fetching instructions from the instruction cache (which is filled from memory if there are no instructions in it).
	developer.apple.com /dev/techsupport/develop.mactech/issue_16/Radcliffe_final.html (9026 words)

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