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Topic: Instruction scheduling

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	Encyclopedia :: encyclopedia : Instruction (Site not responding. Last check: 2007-11-01)
		An instruction is a form of communicated information that is both command and explanation for how an action, behavior, method, or task is to be begun, completed, conducted, or executed.
		A portion (field) of the instruction designates the operation to be done and is called an opcode; since the numeric value of this is not very meaningful to humans, a corresponding short abbreviation is used by programmers.
		The size, or "width" of an instruction depends on the architecture of the platform, but it is usually from 4 to 64 bits wide.
	www.hallencyclopedia.com /Instruction (290 words)

	Instruction scheduling - Wikipedia, the free encyclopedia
		Instruction scheduling is typically done on a single basic block.
		Instruction scheduling may be done either before or after register allocation or both before and after it.
		If scheduling is only done after register allocation then there will be false dependencies introduced by the register allocation that will limit the amount of instruction motion possible by the scheduler.
	en.wikipedia.org /wiki/Instruction_scheduling (494 words)

	Untitled Document
		The instruction is executed as soon as it has been decoded, causing the appropriate modification to the instruction counter which indicates the location from which the sequencing matrices are to replenished.
		The other types of branch instructions, where the branch address and/or the question of whether the branch is to be taken cannot be determined directly from the instruction, but rather depend on the contents of one or more registers, cause rows to be entered into the sequencing matrices in the usual way.
		When the instruction scheduler initiates execution of a load or store instruction the rows corresponding to the instruction are removed from the S and D matrices, and the B vector (except for the last element, corresponding to the store) is updated in the usual way.
	ai.eecs.umich.edu /~mirror/ACS/DISpaper/DynInstSched-paper.html (4515 words)

	Explicitly Parallel Instruction Computing - Wikipedia, the free encyclopedia
		One goal of this strategy is to move the complexity of instruction scheduling from the CPU hardware to the software compiler, which can do the instruction scheduling statically (with help of trace feedback information).
		As wider implementations (more execution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
		Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions.
	en.wikipedia.org /wiki/Explicitly_Parallel_Instruction_Computing (769 words)

	Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler - ... (Site not responding. Last check: 2007-11-01)
		The instruction scheduling function is the modulo scheduling function of an optimizing compiler and it is noted that the time-reverse transforms preserve all modulo constraints.
		The modulo schedule is derived by traversing the data dependency graph for the loop assigning time-stamps to the instructions.
		This time-reversed schedule is then mapped back to physical time values representing the usual forward-scheduling scheme for the instructions in the data dependency graph but with the difference that the time-reversed scheduling operation has has created a better schedule of instructions.
	www.freepatentsonline.com /5867711.html (6208 words)

	Program Optimisation Catalogue - Instruction Scheduling (Site not responding. Last check: 2007-11-01)
		Instruction scheduling is the movement of low-level instructions whilst preserving the program's meaning.
		Instruction scheduling is constrained by the dependencies between instructions preventing arbitrary reordering.
		Instruction scheduling is an NP-hard problem, and hence heuristic algorithms must be used.
	users.chariot.net.au /~matty/optcat/instruction_scheduling.html (270 words)

	Instruction Scheduling Using Integer Programming (Site not responding. Last check: 2007-11-01)
		Instruction scheduling is one of the most important, if not the most important, compiler optimizations.
		Because the instruction scheduling problem is NP-complete, limited research has been done on optimal instruction scheduling.
		However, because in practice instruction scheduling problems contain a significant amount of structure, it is possible that these problems can be solved in reasonable (lower-polynomial) time.
	www.ucop.edu /research/micro/abstracts/98_172.html (235 words)

	Citations: Efficient Instruction Scheduling Using Finite State Automata - Bala, Rubin (ResearchIndex) (Site not responding. Last check: 2007-11-01)
		In the Co scheduling method, a single path in the MS state diagram, and the time steps corresponding to it are used to guide the software pipelining method.
		In the context of Co scheduling, the MS state diagram may consist of a large number of paths especially for large values of the loop initiation interval (II) One basic observation that we make in this paper is that a significant number of....
		For each instruction class I such that the [I; 0]th entry in a state matrix is 0, the initiation of an instruction belonging to class i is legal and causes a state transition to a new state....
	sherry.ifi.unizh.ch /context/14803/205264 (3819 words)

	UNCW - Randall Library (Site not responding. Last check: 2007-11-01)
		All scheduling is handled on a first-come, first-served basis and precedence is given to library instruction taught by UNCW librarians.
		Sessions scheduled in the Library Instruction Classroom should be limited in size to 30 participants, due to the limited number of computer workstations.
		Please provide the following information in order to have a session scheduled: campus phone number, the number of students in class, length of class, a date when you would like to bring your class in (and a backup date), and be able to provide us with a copy of the research assignment.
	library.uncwil.edu /web/policies/instructionscheduling.html (298 words)

	VLIW Processors and Trace Scheduling
		In trace scheduling code the added compensation code was not compacted, but would undergo scheduling when the trace containing it was compacted.
		The scheduler considers each node in turn and decides the functional unit, data path to deliver the operands, register bank to hold the result and cycles on the schedule where the operand may be placed.
		If a naive instruction encoding is used binaries containing instruction words with a fixed number of opcodes cannot be executed on another processor of the same family with a different number of execution units.
	www.cs.utah.edu /~mbinu/coursework/686_vliw/old (4469 words)

	GNU Compiler Collection - Wikipedia, the free encyclopedia
		The behavior of the GCC back end is partly specified by preprocessor macros and functions specific to a target architecture, for instance to define the endianness, word size, and calling conventions.
		The exact set of GCC optimizations varies from release to release as it develops, but includes the standard algorithms, such as jump optimization, jump threading, common subexpression elimination, instruction scheduling, and so forth.
		The final phase is somewhat anticlimactic, since the patterns to match were generally chosen during reloading, and so the assembly code is simply built by running substitutions of registers and addresses into the strings specifying the instructions.
	en.wikipedia.org /wiki/GNU_Compiler_Collection (1159 words)

	Instruction Scheduling
		For example if an instruction needs a value from a previous instruction it must appear after it in the code stream.
		All modern processors use instruction-level parallelism techniques such as pipelining, very long instruction word (VLIW) or superscalar technology, and so can be working on multiple instructions at the same time.
		Instruction scheduling is an NP-hard problem, and hence heuristics must be used.
	users.chariot.net.au /~matty/ultra/optcat/Instruction_Scheduling.html (270 words)

	Optimal instruction scheduling and register allocation
		Optimal contiguous schedules are mostly good (but not necessarily globally optimal) schedules with regard to the register need, but they are less suitable with respect to the execution time of the schedule on a pipelined or superscalar target processor.
		A chapter on optimal instruction scheduling for basic blocks is provided in Chapter 2 of my habilitation thesis (appeared in Dec.\ 2000).
		Used in a project (1997) for instruction scheduling and register allocation for a digital signal processor, by Daniel Kästner and Marc Langenbach (at Reinhard Wilhelm's group for compiler construction at the computer science department of the University of Saarbrücken).
	www.ida.liu.se /~chrke/regalloc.html (858 words)

	instructions from FOLDOC
		The compiler phase that orders instructions on a pipelined, superscalar, or VLIW architecture so as to maximise the number of function units operating in parallel and to minimise the time they spend waiting for each other.
		Examples are filling a delay slot; interspersing floating-point instructions with integer instructions to keep both units operating; making adjacent instructions independent, e.g.
		The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.
	ftp.sunet.se /foldoc/foldoc.cgi?instructions (329 words)

	Graph-Partitioning Based Instruction Scheduling (ResearchIndex) (Site not responding. Last check: 2007-11-01)
		The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques and a scheduling phase that integrates register allocation and spill code generation.
		The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated.
		1 Modulo Scheduling for a Fully-Distributed Clustered VLIW Arc..
	citeseer.ifi.unizh.ch /641526.html (580 words)

	Library Instruction Scheduling Form
		This form is for requesting an instruction session for English 1105, 1106, or H1204 or Communication Studies 1105 or 1106
		Library sessions will be most effective if scheduled after the research assignment has been communicated to students and after students have had time to develop an initial research topic so that the students can use these topics as sample searches during the session.
		Include relevant texts, the number and scope of required sources, and when this assignment is due.
	www.lib.vt.edu /services/forms/instructsched.php (144 words)

	Lovejoy Library's Instruction Program (Site not responding. Last check: 2007-11-01)
		Email Lydia Jackson, Instruction and Reference Librarian, at ljackso@siue.edu or Matthew Schmitz, Reference and Instruction Specialist, at maschmi@siue.edu.
		Sessions are scheduled on a first come-first serve basis with at least two weeks notice preferred.
		All instruction sessions are scheduled following the library guidelines and policies.
	www.library.siue.edu /lib/library_services/instruction/scheduling_session.html (66 words)

	Instruction scheduling in the TOBEY compiler
		This fine-grain parallelism cannot always be achieved by the processor alone, but relies to some extent on the ordering of the instructions in a program.
		This dependence implies that optimizing compilers for these processors must generate or schedule the instructions in an order that maximizes the possible parallelism.
		This paper describes the parts of the TOBEY compiler which address the instruction scheduling issue.
	www.research.ibm.com /journal/rd/385/blainey.html (122 words)

	Retargetable Instruction Scheduling for Pipelined Processors - Bradlee (ResearchIndex) (Site not responding. Last check: 2007-11-01)
		Abstract: Retargetable Instruction Scheduling for Pipelined Processors by David Gordon Bradlee Chairperson of the Supervisory Committee: Professor Susan J. Eggers Department of Computer Science and Engineering Retargetable code generators for complex instruction set computers (CISCs) have focused on sophisticated pattern matching code selection, because CISCs provide many machine instruction sequence choices.
		76 Efficient instruction scheduling for a pipelined architectur..
		8 The GNU instruction scheduler (context) - Tiemann - 1989
	citeseer.ist.psu.edu /bradlee91retargetable.html (1484 words)

	EPIC Instruction Scheduling Based on Optimal Approaches - Haga, Barua (ResearchIndex)
		Abstract: This paper presents a method for instruction scheduling that considers the scheduling restrictions inherent in VLIW processors, particularly EPIC.
		EPIC architectures have the potential to offer substantial speedups versus superscalars; however, development of a number of new compiler technologies, such as improved instruction scheduling, is critical to EPIC's success.
		EPIC imposes restrictions on the nature and code-order of the instructions that can issue together in the same cycle.
	citeseer.ist.psu.edu /haga01epic.html (422 words)

	Superscalar RISC instruction scheduling (US6289433) (Site not responding. Last check: 2007-11-01)
		Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
		Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
		Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
	www.delphion.com /details?pn=US06289433__ (1728 words)

	Scheduling Visits & Instruction K-12, Texas Tech University Libraries (Site not responding. Last check: 2007-11-01)
		The University Library is a busy research environment that serves a campus of around 30,000 students, faculty, and staff. We are dedicated to providing the best possible research experience for your students. In order to accommodate the needs of both campus patrons and visitors, the following group visitation policies are in place:
		visits should be scheduled at least two weeks in advance
		visitations may not be scheduled during Finals periods due to heavy research and study demands placed upon campus students at the end of semesters
	library.ttu.edu /ul/instruction/sched.php (234 words)

	Assembler (Site not responding. Last check: 2007-11-01)
		Assemblers are far simpler to write than compilers for high-level languages, and have been available since the 1950s.
		Modern assemblers, especially for RISC based architectures, such as MIPS, Sun SPARC and HP PA-RISC, optimize instruction scheduling to exploit the CPU pipeline efficiently.
		High-level assemblers provide high-level-language abstractions such as advanced control structures, high-level procedure/function declarations and invocations, and high-level abstract data types including structures/records, unions, classes, and sets.
	www.freedownloadsoft.com /info/assembler.html (507 words)

	block scheduling (Site not responding. Last check: 2007-11-01)
		What is block scheduling and why is it being used in many high schools in the United States?
		Indicator 1: Teachers use the target language as the principal medium of instruction and classroom management.
		Standard 9: Teachers understand the sequential nature of the second language curriculum and articulate the instructional program accordingly.
	www4.ncsu.edu /~navey/blksch.htm (404 words)

	The Experimental Computing Laboratory
		Synthesizing Variable Instruction Issue Interpreters for Implementing Functional Parallelism on SIMD Computers," IEEE Transactions on Parallel and Distributed Systems, Volume 8, Number 4, 412-423, April 1997.
		N. Abu-Ghazaleh, and P. Wilsey, "Variable Instruction Scheduling for MIMD Interpretation on Pipelined SIMD Machines and for Compositional Instruction Sets," Concurrency-Practice and Experience, Volume 9, Number 1, 31-39, January 1997.
		Scheduling Time Warp Processes using Adaptive Control Techniques," 1994 Winter Simulation Conference, J. Tew, S. Manivannan, D. Sadowski, and A. Seila (eds), 731-738, December 1994.
	www.ece.uc.edu /~paw/lab/pubs.html (4521 words)

	Scheduling an Instruction Session (Site not responding. Last check: 2007-11-01)
		To schedule an instruction session for your students, call University Libraries Instructional Services (285-8017) at least two weeks in advance (just one week in the summer).
		What is the assignment related to the instruction?
		Note: Instruction sessions are scheduled on a first come, first served basis. The earlier in the semester you call, the better your chances of getting the date(s) you want.
	www.bsu.edu /library/article/0,1894,203858-14042-34992,00.html (108 words)

	Instruction scheduling method patent invention
		Click on the above for other options relating to this Instruction scheduling method patent application.
		Each week you receive an email with patent applications related to your keywords.
		Thank you for viewing the Instruction scheduling method patent info.
	www.freshpatents.com /Instruction-scheduling-method-dt20060518ptan20060107267.php (261 words)

	Research projects
		Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism, J.L. Lo and S.J. Eggers, Conference on Programming Language Design and Implementation (June 1995).
		Balanced Scheduling: Instruction Scheduling When Memory Latency is Uncertain, D.R. Kerns and S.J. Eggers, Conference on Programming Language Design and Implementation (June 1993).
		The Marion System for Retargetable Instruction Scheduling, D.G. Bradlee, R.R. Henry, and S.J. Eggers, Conference on Programming Language Design and Implementation (June 1991).
	www.cs.washington.edu /homes/eggers/Research/cs.html (127 words)

	Instruction Scheduling (Site not responding. Last check: 2007-11-01)
		This research focus on novel techniques for instruction scheduling with special emphasis on modulo scheduling.
		"Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture"
		"The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures"
	people.ac.upc.edu /antonio/pipe.html (164 words)

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