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Topic: Instruction set architectures


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RTL

In the News (Thu 25 Apr 19)

  
  BDTI - DSP Dictionary
Instruction set A processor's instruction set is the set of assembly language instructions that it is able to execute.
Instruction set simulators provide a software view of the processor; that is, they display program instructions, registers, memory, and flags, and allow the user to manipulate the register and memory contents.
Von Neumann architecture A processor memory architecture in which there is a single memory bank and single bus for transferring both instructions and data.
www.bdti.com /articles/dspdictionary.html   (1817 words)

  
 CGEN: RTL
An example of an architecture with more than one is the ARM which has a 32 bit instruction set and a 16 bit "Thumb" instruction set (the sizes here refer to instruction size).
If the architecture has a variable length instruction set, this is the size of the initial word to fetch.
An architecture may have multiple endiannesses, including one for each of: instructions, integers, and floats (not that that's intended to be the complete list).
sources.redhat.com /cgen/docs-1.0/cgen_3.html   (5277 words)

  
 The Lisp Machine
Instruction emulation-- When the Lisp Machine hardware encounters an exceptional situation (for example, an integer arithmetic operation that exceeds the hardware imposed implementation limit or an operation on a software-defined type) the hardware traps out to a software "emulator" subroutine.
Early Lisp Machines implemented their micro-programmed architectures with a writable control store, which meant the instruction set, and to a certain extent other architectural features of the machine, could be changed by simply writing, compiling, and loading new micro-code.
Architecture research papers continue to evaluate the merits of read and write "barriers", pioneered by Lisp Machine garbage collectors to track object references and speed automatic storage reclamation, and "fast traps" to allow expeditious handling of exceptional conditions in a manner similar to the Lisp Machine instruction emulation.
pt.withy.org /publications/LispM.html   (1838 words)

  
  ISAExtensions   (Site not responding. Last check: )
The constant dependency set is the union of the the constant dependency set of the enumerated left array element and the constant dependency set of the enumerated right array element.
In the case where the instruction count of the left and right children are both 0 and the left and right children are not leaf nodes, the instruction saved field is incremented by 1 since the new instruction is composed of two existing instructions.
Instructions such as these could be implemented, but the instruction could be considered to alter the state of the machine since the instruction would change the flow of the program.
www.eecs.berkeley.edu /~sjweber/244/isaextensions.html   (5740 words)

  
  Instruction set   (Site not responding. Last check: )
An instruction set, or instruction set architecture (ISA, but not to be confused with the ISA motherboard bus), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any).
An ISA is a specification of the set of all binary codes (opcodes) that are the native form of commands implemented by a particular CPU design.
"Instruction set architecture" is sometimes used to distinguish this set of characteristics from the microarchitecture, which is the set of processor design techniques used to implement the instruction set (including microcode, pipelining, cache systems, and so forth).
www.punweb.com /article/Instruction_set_architecture   (599 words)

  
 Instruction set Summary
An instruction set, or instruction set architecture (ISA, but not to be confused with the ISA motherboard bus), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any).
An ISA includes a specification of the set of all codes (opcodes) that are the native form of commands implemented by a particular CPU design.
"Instruction set architecture" is sometimes used to distinguish this set of characteristics from the microarchitecture, which is the set of processor design techniques used to implement the instruction set (including microcode, pipelining, cache systems, and so forth).
www.bookrags.com /Instruction_set   (1948 words)

  
 i386 and x86-64 Options - Using the GNU Compiler Collection (GCC)
Use scalar floating point instructions present in the SSE instruction set.
This instruction set is supported by Pentium3 and newer chips, in the AMD line by Athlon-4, Athlon-xp and Athlon-mp chips.
The earlier version of SSE instruction set supports only single precision arithmetics, thus the double and extended precision arithmetics is still done using 387.
gcc.gnu.org /onlinedocs/gcc-3.4.4/gcc/i386-and-x86_002d64-Options.html   (1891 words)

  
 National Semiconductor Embedded Microcontrollers - Microcontroller.com
The CompactRISC architecture is enhanced with some typical CISC features, like variable instruction set and direct memory bit manipulation to make it even more effective for embedded applications.
Traditional RISC architectures are driven by the need to squeeze every bit of execution time from a fast system clock, hence typically trading silicon efficiency for instruction execution efficiency.
Instructions for the CompactRISC architecture may be 2, 4 or 6 bytes long, but basic instructions are only 2 bytes long.
www.microcontroller.com /Embedded.asp?did=111   (1796 words)

  
 Benchmarking the MAXQ Instruction-Set Architecture vs. RISC Competitors - Maxim/Dallas
The MAXQ instruction set is founded upon the transfer-trigger concept.
The best way to compare instruction-set architectures is to define some set of tasks and write the code to perform those tasks.
When comparing architectures, the average performance in MIPS is often much less than the peak performance (MIPS) and varies depending upon instruction mix.
www.maxim-ic.com /appnotes.cfm/appnote_number/3221   (3110 words)

  
 Instruction Set Architecture (ISA)   (Site not responding. Last check: )
The Instruction Set Architecture (ISA) is the part of the processor that is visible to the programmer or compiler writer.
Instructions were of varying length from 1 byte to 6-8 bytes.
The ISA is composed of instructions that all have exactly the same size, usualy 32 bits.
shekel.jct.ac.il /~citron/ca/isa.html   (904 words)

  
 IBM RD 50-2/3 | High-quality ISA synthesis for low-power cache designs in embedded microprocessors
A hardware extension of this technique is to use echo instructions [12], which indicate where the abstracted code sequence is located and the number of instructions to be executed.
Instruction coalescing [20] extends the Thumb architecture with augmenting instructions that allow the execution of two 16-bit Thumb instructions as a single 32-bit ARM instruction.
Since the instructions are half the size, the cache lines can be viewed as being twice the size (this operates much like a next-line prefetch on cache miss) because twice the number of instructions are brought into the cache (i.e., fewer compulsory misses and, for displaced lines, fewer conflict misses to restore the instructions).
www.research.ibm.com /journal/rd/502/cheng.html   (5674 words)

  
 EETimes.com - Embedded wireless networking drives new ISAs for MCUs
Instruction set architectures, tuned specifically for wireless and other network traffic and computing models, are now coming to market that make processing of packets more efficient and easier to develop and program applications for networked embedded systems.
By comparison, in the standard MIPS instruction set architecture four operations are required to move data to and from memory and to increment the addresses in which separate instructions are needed to move the data to and from memory, and to increment the addresses.
A complete set of logical, arithmetic and shift instructions, in addition to basic bit test and set instructions, are required to enable efficient program loops based on arbitrary streams of data, and quick access via masks to specific header values.
www.eetimes.com /story/OEG20030221S0036   (1513 words)

  
 CISC Technoloty - Complex Instruction Set Computer - Computer Fundamentals - Computer Science Tutorials - Provided by ...
Because instructions could be retrieved up to 10 times faster from a local ROM than from main memory, designers began to put as many instructions as possible into microcode.
The instruction is decoded: the controlling code from the microprogram identifies the type of operation to be performed, where to find the data on which to perform the operation, and where to put the result.
So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length---this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine.
www.laynetworks.com /CISC.htm   (1684 words)

  
 S/390 microprocessor design
This requires relatively complex instruction fetching and decoding logic to handle the different instruction lengths and the large instruction set, as well as some form of internal code to deal with operations too complex for hard-wired execution logic.
Although relative branch instructions, in which the branch target is specified as an offset from the current instruction address, have been added to ESA/390, these are not yet in widespread use, and the vast majority of the branches executed on S/390 computers use a general register to specify the target address.
This may be contrasted with a design for an ISA in which indirect branches are the exception rather than the rule; in the latter case, the branch target address can generally be computed by adding the specified offset to the current instruction address, with no register file access required and no interlock against prior instructions.
www.research.ibm.com /journal/rd/446/webb.html   (4897 words)

  
 [No title]   (Site not responding. Last check: )
An instruction set processor is a device (or model) that interprets some of the data in a memory as instructions that specify the operations that the processor does.
Instructions appear in memory as bit strings or numbers comprised of one or more consecutive cells.
The set of instructions' interpretations as operations is part of the machine language or instruction set architecture.
www.cs.albany.edu /~sdc/csi504/Lect07   (379 words)

  
 Lecture 2
Thus far we have seen two different instruction set architectures: the 68000 and the simple instruction set we used in the lectures where we explained how a CPU can be designed.
In this lecture we will discuss a few of the attributes that can be used to characterize these instruction sets in a meaningful way.
In one way or another, virtually all instruction sets that exist today can be classified using these attributes.
www.eecg.toronto.edu /~moshovos/ECE243-06/l23-instruction-set-characterization.html   (470 words)

  
 RISC for Graphics: A Survey and Analysis of Multimedia Extended Instruction Set Architectures
Using the select field of the instruction, a single subword is selected from the second source register and is used as a scalar in the operation on the vector.
Regardless of whether the programmer chooses to call assembly instructions directly or call them from C macros, he or she must be prepared for a significant amount of additional coding effort.
A single unpacking instruction was required at the end of the unrolled loop in Box 1, hence preventing the reduction from being an ideal 50%.
www.tc.umn.edu /~erick205/Papers/EE8362/8362Paper.html   (5232 words)

  
 The Ultimate RISC
The Nova has an instruction set in which most instructions can execute in a single fixed-length cycle involving an instruction fetch, and one of either a fetch, a store, or an operation on registers.
This is a complex instruction with 3 address fields (reducable to two if an accumulator is used), and the conditional branch phase of each instruction cycle depends on the results of the subtract phase of that instruction, inhibiting pipelined execution.
The control unit for the instruction execution unit shown in Figure 2 is quite simple both because there is no problem of opcode decoding and because there are no conditional operations in the instruction execution cycle.
www.cs.uiowa.edu /~jones/arch/risc   (2609 words)

  
 ARM Instruction Set Architecture | ARM Instruction Set Architecture   (Site not responding. Last check: )
It was the first ISA to include the Thumb instruction set which made it possible to store parts of the code as 16-bit instructions, thus saving memory space.
To run Thumb instructions the processor has to switch to Thumb mode, and then back to ARM mode to run full 32-bit instructions.
ARMv7 is the instruction set in the ARM Cortex family, and the latest instruction set from ARM.
www.sevensandnines.com /p135909/p135909_eng.php   (248 words)

  
 Patents: 5430862
The core 114 is capable of native instructions from a predetermined set of micro-controller specific instructions.
One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register s...
A method for addressing internal instructions in an out-of-order processor is proposed, which allows for an efficient register renaming even in case internal instructions are issued to a multitude of window buffers.
www.freepatentsonline.com /REF5430862   (1733 words)

  
 The Symbolics Virtual Lisp Machine
With the multiple-issue instruction execution we were able to take the approach of using the Alpha as a programmable micro-engine and write the emulation of the Lisp Machine instruction set as if we were writing micro-code.
The memory architecture is "object-oriented"- every memory word contains an object in the form of a data-type (tag) and representation, either immediate (data) or as a reference (pointer) to the representation of the object.
Today, advanced compiler technology appears to obviate the need for microcoding and complex instruction sets, but we discovered that the continual climb in processor clock rates (and resulting increasing mismatch between memory speeds and instruction execution rate) may mark the return of micro-programming as a valid implementation technology.
pt.withy.org /publications/VLM.html   (1698 words)

  
 The ARM Instruction Set Architecture
The ARMv4T architecture added the 16-bit Thumb® instruction set which enabled compilers to generate more compact code (memory savings of up to 35% over the equivalent 32-bit code), while retaining all the benefits of a 32-bit system.
All ARMv7 architecture profiles implement Thumb® -2 technology which is built on the foundation of the ARM industry-leading Thumb code compression technology, while retaining complete code compatibility with existing ARM solutions.
ARM NEON technology is an architecture option with the ARMv7A architecture and is designed to address the demands of next generation high-performance, media intense, low power mobile handheld devices.
www.arm.com /products/CPUs/architecture.html   (1268 words)

  
 [No title]
So, an instruction like "add this byte from memory to register 1" from a CISC instruction set would need two instructions in a load-store architecture: "load this byte from memory into register 2" and "add register 2 to register 1".
The control line for this MUX is not shown, but would come from the ID phase and is based on the instruction type (it will select (9) for instructions that operate on two registers, and (6) for instructions that work one one register and one immediate value).
To illustrate this point, watch the execution of a single instruction in the non-pipelined and in the pipelined processor.
www.web-ee.com /primers/files/MIPS/MIPS.htm   (4020 words)

  
 Architectures for Conversation (ii): What Communities of Practice can mean for Information Architecture » ...
Slide 1: Architectures for Conversation (ii) What Communities of Practice can mean for IA (and UX in general, for that matter) Andrew Hinton April 2007 www.inkblurt.com This is a talk I put together for the Philly CHI group.
For one thing, it arose in a very homogeneous community of engineers, academics, etc, who all knew one another professionally in one way or another, and who had a sort of cultural baseline they were communicating from.
Because architecture is about creating structures that enable people to better inhabit spaces.
www.slideshare.net /andrewhinton/architectures-for-conversation-ii-what-communities-of-practice-can-mean-for-information-architecture   (6922 words)

  
 rtos, embedded system, Embedded Industry Partners - Green Hills Software
We have helped many new architectures take off in the market place.
DSP Chips require a new paradigm for compiling and debugging.
SimEXT – Model user defined instructions from Green Hills or third party simulators.
www.ghs.com /ces   (667 words)

  
 Architectures and Compilers to Support Reconfigurable Computing
For parallel computations, acceleration is achieved through the exploitation of the parallelism in a program and its mapping onto an architecture of various processors, but for RC it is achieved through the migration of the most computationally-intensive parts of the program to RPUs.
Each hardware image related to a configuration is described in VHDL, which defines the units used from the library set, the interconnections between them, and when the scheduling of operations is necessary, the control part (sharing of resources such as operators or memory access units).
Definition in [10]: ``A transformation of a behavioural description into a set of connected storage and functional units''.
www.acm.org /crossroads/xrds5-3/rcconcept.html   (4168 words)

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