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	Instructions Per Clock - Wikipedia, the free encyclopedia
		Instructions Per Clock is a technical term from computing that is used to describe one aspect of a processor's performance: the average number of individual assembler instructions executed for each clock cycle.
		The number of instructions per second for a processor can be derived by multiplying the instructions per clock and the clock speed (measured in cycles per second or Hz) of the processor in question.
		The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierachy.
	en.wikipedia.org /wiki/Instructions_Per_Clock (526 words)

	[No title]
		Once the instruction starts advancing through the pipeline again, the gaps in the pipeline that were created by the stall, gaps that are commonly called "pipeline bubbles," travel down the pipeline ahead of the formerly stalled instruction until they eventually leave the pipeline.
		clock, for an average instruction throughput of 0.7 instructions per clock.
		For each clock in which there's a bubble in the write stage, the pipeline's instruction throughput is 0 instructions/clock so its average instruction throughput for the whole period continues to decline.
	arstechnica.com /articles/paedia/cpu/pipelining-2.ars/3 (1319 words)

	Instructions Per Clock: Dictionary definition
		Instructions Per Clock is a technical term to describe one aspect of a processor performance: the average number of individual assembler instructions execute for each clock cycle.
		A processor performance can be computed multiplying its clock speed by the IPC: the same performance can be derived from a high IPC and a relatively low clock speed (like the AMD Athlon, or HP PA-RISC), or from a low IPC and higher clock speed (like the Intel Pentium 4 and DEC Alpha).
		In particular, the speed-demon design of the Intel Pentium 4 is often cited by AMD fans as "cheating", since the higher clock speed rating makes the processor appear faster to the general, non-expert audience.
	www.encyclopedian.com /in/Instructions-Per-Clock.html (202 words)

	Dictionary of Meaning www.mauspfeil.net (Site not responding. Last check: 2007-10-16)
		The number of instructions per second for a processor can be derived by multiplying the instructions per clock and the clock speed (measured in cycles per second or Hertz Hz) of the processor in question.
		A given level of instructions per second can be achieved with a high IPC and a low clock speed (like the AMD Athlon, Hewlett-Packard HP PA-RISC, or Sun Microsystems SPARC), or from a low IPC and high clock speed (like the Intel Pentium 4 or DEC Alpha).
		The manufacturers of speed-demon designs tend to prefer to quote the clock speed in their consumer marketing literature (for example "this is the latest 3.2 GHz model").
	www.mauspfeil.net /Instructions_Per_Clock.html (560 words)

	Superscalar
		The term is a modification of scalar, processors that run one instruction per clock cycle, themselves a step up from earlier processors that would take a variable number of cycles to complete any given operation.
		The dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to the two units.
		One potential solution to this problem is to move the dispatcher logic out of the chip and into the compiler, which can spend considerably more time and effort on making the best decisions possible.
	www.sciencedaily.com /encyclopedia/superscalar (519 words)

	Inside the Origin2000 Processor (Site not responding. Last check: 2007-10-16)
		This clock and its speed are very important to the performance of the Origin2000 as the clock is used to synchronize events that take place within the processor, which has a direct impact on the speed at which the processor completes instructions.
		The MIPS R10000 processors are capable of fetching and decoding four instructions per clock cycle.
		Sometimes the processor executes an instruction for a conditional branch to a different part of a program, but the information on which to base the decision as to whether or not to branch is not yet available.
	www.ualberta.ca /CNS/RESEARCH/General/OLD/processor.html (782 words)

	Real World Technologies - Alpha EV8 (Part 3): Simultaneous Multi-Threat
		IPC can be lost due to the lack of ILP (instruction level parallelism) in the program instruction stream or the inability to exploit the ILP that is present due to limitations in the processor.
		Issue IPC includes instructions that are issued, partially executed, and then squashed due to branch misprediction or other reasons, as well as those that execute to completion.
		If the IPC of our hypothetical EV8 on a specific program is 2.5, that means on average, 5.5 opportunities to execute an Alpha instruction are lost every clock cycle.
	www.realworldtech.com /page.cfm?articleid=RWT011601000000 (560 words)

	Patent 5559986: Interleaved cache for multiple accesses per clock cycle in a microprocessor
		The multiple data accesses per clock are made possible because the data cache of the present invention is interleaved.
		2, microprocessor 200 generally comprises a prefetcher or instruction cache means 201 for prefetching instructions from main memory to be executed by a microprocessor 200 and an instruction decoder 202 coupled with prefetcher 201 for decoding the instructions fetched by prefetcher 201.
		Thus, the present invention is not limited to two simultaneous data accesses per clock nor is it required to have the same number of data references as execution pipelines.
	www.freepatentsonline.com /5559986.html (6381 words)

	Instructions per clock (John R. Mashey)
		The reasoning was: a) On any given date, vendors might have different clock rates, and performance is affected by clock rates.
		Of course: d) Some architectures need more instructions to accomplish the same work, so it is hard to compare between different instruction set architectures.
		In general, the scalability of a design (which was what IPC was trying to get at, i.e., what would be achieved by better processes) is not determined by the number of gate delays in most paths, but by the number of gate delays in the slowest path, and it only takes one.
	yarchive.net /comp/instr_per_clock.html (946 words)

	[No title]
		Instead, the fetch groups are alternately* passed one at a time into the decode/dispatch stages, so that only five instructions per cycle ó all from a single thread ó are dispatched to the core's issue queues.
		The fact that the issue queues will be populated by instructions from two different threads probably lessens the chances of this degenerate case occurring, thus providing a boost to execution unit utilization.
		The chip simply controls the decode rate of instructions from the two threads, decoding more of the instructions from the higher-priority thread than from the lower-priority thread on each cycle.
	arstechnica.com /articles/paedia/cpu/mpf-2003.ars/1 (1084 words)

	[No title]
		There are some practical limits to how many instructions can be executed in parallel, so the processor doesn't always reach the ideal completion rate of two instructions per clock.
		Sometimes, the processor can't find two instructions to execute in parallel on a particular cycle, which means that it must insert a pipeline bubble into one of the pipelines on that cycle, bringing the completion rate down.
		When the processor is executing two threads simultaneously, and one of the threads stalls in the fetch stage (i.e., there's a cache miss so the thread must fetch instructions or data from main memory), the processor can continue normally executing the non-stalled thread.
	arstechnica.com /articles/paedia/cpu/pipelining-2.ars/5 (876 words)

	IPC - Instructions Per Clock, InterProcess Communication
		Instructions Per Clock is not the only word formed from IPC.
		Typical IPC methods include the use of shared memory, pipes, message queues, and sockets.
		Messages can be either blocks of data and information packets, or instructions and requests for process(es) to perform actions.
	www.auditmypc.com /acronym/IPC.asp (322 words)

	Intel Prescott P4 3.2GHz and P4 EE 3.4GHz (Site not responding. Last check: 2007-10-16)
		During the course of the year in 2003, AMD and Intel were engaged in a rigorous competition of raw MHz versus IPC (instructions per clock cycle) marketing.
		However, that year is quickly evaporating and the Athlon 64's integrated memory controller, 64KB instruction and data caches, and up to 1MB of L2 cache, certainly put the heat on Intel at its launch.
		The only difference here is the clock speed, which is now the highest bin part in Intel's line-up currently at 3.4GHz, as well as it's 2MB of integrated L3 cache.
	www.hothardware.com /viewarticle.cfm?articleid=262&catid=1 (916 words)

	Instructions Per Clock Definition / Instructions Per Clock Research (Site not responding. Last check: 2007-10-16)
		Instructions Per Clock is a technical term from computingOriginally, the word computing was synonymous with counting and calculating, and a computer was a person who computes.
		Since the advent of the electronic computer, it has come to additionally mean the operation and usage of these machines, the electrical processes carried out within the computer hardware itself, and the theoretical concepts governing them (computer science)....
		instructions per clock is the way to measure PC performance.
	www.elresearch.com /Instructions_Per_Clock (165 words)

	Flexbeta -> Overclocking Guide & FAQ
		A clock cycle is a period of time in which a processor can carry out a given amount of instructions.
		The higher rate of cycles per clock gives it a better chance of having the memory cycles line up with the CPU cycles, which equates to better performance.
		A memory divider determines the ratio of the memory clock speed to the FSB.
	www.flexbeta.net /forums/index.php?showtopic=5743 (7322 words)

	Geek.com Geek News - Intel's Prescott may be slower than Northwood (Site not responding. Last check: 2007-10-16)
		This is because the IPC is governed by the number of executable units multiplied the number of cycles each instruction takes per stage to be executed over by the length of the pipeline * by Hz.
		IPC or instructions per clock is not dependent on the length of the pipeline but the time it takes to complete individual stages and the number of instructions that can be executed at any point in time.
		IPC is dependent on the number of instructions that can be executed at any point in time and the time they take to complete.
	www.geek.com /news/geeknews/2004Jan/bch20040116023472.htm (11301 words)

	Instructions Per Clock (Site not responding. Last check: 2007-10-16)
		It is suspected that this is the real reason of AMD PR-rating scheme, where the name of each processor isn't equal to the real clock speed anymore.
		All is still licensed under the GNU FDL.
		The scent of magic flowed from these behold, here a source seemed to spring forth, here a messenger seemed where the rumour of Buddha was heard, everywhere in the lands of India, Brahmans' sons of the towns and villages every pilgrim and stranger was.
	www.termsdefined.net /in/instructions-per-clock.html (395 words)

	Thoughts on AMD's Hammer chip
		It seems to me that a better approach to reducing the penalty of poor instruction parallelism would be to just decode more instructions per clock cycle.
		It would likely allow Hammer to decode four instructions per clock cycle much of the time, rarely less than three, and Hammer has the ability to execute 3 instructions per clock cycle.
		The second drawback is execution latency, or the number of clock cycles it takes to decode and execute an instruction, and the negative effect that high latency has on dependant instruction, or instruction which depend on the execution of previous instruction(s) before they can be executed.
	www.theinquirer.net /?article=5165 (994 words)

	Geek.com Geek News - Intel's Prescott may be slower than Northwood
		IPC is different because it is about the number of instructions that can be executed at once (in parallel).
		In contrast, IPC can be compared to a parallel circuit, where there are different paths that the electron can take, but it passes through different loads than another electron may, and ends up in the same place once completing the circuit.
		IPC is really dependent on the number of pipelines as well (not to get that confused with the length of the pipeline).
	www.geek.com /news/geeknews/2004Jan/bakk/wbc20040116023472.htm (15044 words)

	Beto Borbolla's Weblog : Beto Borbolla's Weblog
		When Intel introduced the 486 processor, it came with a 100 percent increase in the number of instructions executed per clock cycle compared to the 386 processor that preceded it.
		The Pentium Pro had a 40 percent increase in instructions per clock cycle over the Pentium.
		And the Pentium 4 is worst of all, rated at 10 percent FEWER instructions per clock cycle than the Pentium III.
	radio.weblogs.com /0114399/2002/12/27.html (249 words)

	Sharky Extreme - '+$ArtG+' - '+$ArtC+' - '+$ArtN+'
		IA-64 instructions are bundled together when originally compiled, simplifying the process of running multiple instructions at once.
		In contrast, x86 instructions are compiled serially, so in order to make use of multiple pipelines, the CPU essentially has to predict or guess what can run simultaneously down each of its pipelines.
		So by setting up what instructions can be run simultaneously when a program is originally compiled, the EPIC architecture is capable of consistently running more operations per clock than an x86 CPU.
	www.sharkyextreme.com /hardware/roadmaps/intel_server_roadmap_5-2000/2.shtml (478 words)

	MacOPINION : Philip Machanick \| Multithreaded Pentium 4 (Site not responding. Last check: 2007-10-16)
		SMT, on the whole, has the potential to be a gain with a complex processor capable of executing multiple instructions per clock cycle, because it does not add significantly to the complexity, and can even replace some of it.
		If the clock speed is equal, and the average number of instructions per clock cycle were similar, the real multiprocessor would be faster overall.
		On the other hand, simplifying the design by reducing the theoretical maximum number of instructions per clock cycle has effects which are hard to predict, because a small fraction of programs can use a very high number of instructions per clock cycle, even if many can't.
	macopinion.com /columns/intelligence/02/12/16 (1125 words)

	Macworld: News: Microprocessor Forum: IBM talks Power5
		The arithmetic of that is two cores per Power5 processor, four processors per module and 16 modules.
		While no specific Macintosh announcements were made, Sinharoy noted during his presentation that the PowerPC 970, the processor that drives Apple's G5, was derived from the Power4 design, suggesting that such a step would be logical again as IBM engineers refine the Power5 design.
		Sinharoy said that the Power5 is working in IBM's labs now and is on schedule to ship next year; however, he made no mention of benchmark performance or clock speed of the new processor.
	www.macworld.com /news/2003/10/14/power5/index.php?pf=1 (703 words)

	Advanced Architectures - multiple instructions completed per clock cycle
		Independent instructions in the program can be executed in parallel, but not all can be.
		ability of the processor to find independent instructions (the processor needs to look ahead of the current point of execution to locate independent instructions that can be brought into the pipeline and executed)
		The more sophisticated the processor, the less it is bound by the strict relationship between these orderings.
	www.cs.uni.edu /~fienup/cs240s02/lectures/lec6_2-12-02.htm (553 words)

	Encyclopedia: Instructions Per Clock
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		Updated 219 days 6 hours 30 minutes ago.
		Click for other authoritative sources for this topic (summarised at Factbites.com).
	www.nationmaster.com /encyclopedia/Instructions-Per-Clock (247 words)

	MajorGeeks Support Forums - Overclocking Guide
		It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock.
		A one-megahertz clock (1MHz) means some number of bits (16, 32, 64, etc.) are manipulated one million times per second.
		Yes, Hertz is a unit of frequency equal to one cycle per second.
	forums.majorgeeks.com /showthread.php?t=52812 (8387 words)

	Transmeta Corporation : Efficeon > Architecture > 256-bit VLIW Engine (Site not responding. Last check: 2007-10-16)
		To maximize performance and responsiveness, the Efficeon processor features a state-of-the-art 256-bit-wide VLIW (Very Long Instruction Word) engine that can issue up to 8 instructions per clock cycle.
		This hardware engine processes instructions like a conventional processor, but runs a custom, efficient instruction set.
		The addition of these extensions enables multimedia applications to run up to 80% faster per clock cycle than previous generation processors from Transmeta.
	www.transmeta.com /efficeon/vliw.html (242 words)

	DEC Alpha (Site not responding. Last check: 2007-10-16)
		A 64-bit, RISC (reduced instruction set computing) microprocessor from Digital Equipment Corporation (DEC), first introduced in 1992.
		The Alpha is a superscalar, superpipelined design, which allows the processor to execute more than one instruction per clock cycle; it can execute as many as six instructions per clock cycle and can sustain four instructions per clock cycle.
		It has data and instruction caches, a floating-point processor, 64-bit registers, 64-bit data and address buses, and a 128-bit data path between the processor and memory.
	home.comcast.net /~pattman64/Computer.pages/dictionary/Terms/2461HTML-710.html (134 words)

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