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	intel i432 (Site not responding. Last check: 2007-09-07)
		Intel's iAXP-432 MicroMainframe (often known as a "mainframe on a chip") was a four-core, 32-bit microprocessor released in 1981.
		However the design was deathly slow and very expensive, and Intel's plans to replace the x86 architechture with the 432 ended miserably.
		The 960 MC's core was used by Intel to create the i960 RISC CPU, by dropping many of the i432-support from the design.
	www.yourencyclopedia.net /intel_i432.html (734 words)

	intel i960 (Site not responding. Last check: 2007-09-07)
		Intel's i960 (or 80960) was a RISC-based microprocessor design that became quite popular during the early 1990s as an embedded microcontroller, for some time likely the best-selling CPU in that field, pushing the AMD 29000 from that spot.
		In the mid-1980s Intel and Siemens started a joint project to create the BiiN machine, and as a part of this project the i432 was re-built on a RISC core, creating the 960 MC.
		Although the 960 MC was never released commercially, Intel later took the core processor design, dropped the i432 instructions and complex microcode, and was left with a simple but powerful RISC CPU.
	www.yourencyclopedia.net /intel_i960.html (370 words)

	Intel i860 - Wikipedia, the free encyclopedia
		The Intel i860 (also 80860, and code named N10) was a RISC microprocessor from Intel, first released in 1989.
		The i860 was (along with the i960) one of Intel's first attempts at an entirely new, high-end ISA since the failed Intel i432 from the 1980s.
		It was released with considerable fanfare, and obscured the release of the Intel i960 which many considered to be a better design.
	en.wikipedia.org /wiki/Intel_i860 (908 words)

	BiiN - Open Encyclopedia (Site not responding. Last check: 2007-09-07)
		Intel owned all the silicon designs which were licensed to Siemens, while Siemens owned all the software and documentation and licensed them to Intel.
		Like the i432, the 960 MC included tagged memory for complete memory protection even within programs (as opposed to most CPU's, which offer protection only between programs), a full set of instructions for task control, and complex microcode to run it all.
		Unlike the i432, the 960 MC had fairly good performance, mostly as a side effect of dramatically reducing the complexity of the core instruction set, integration of all CPU functions on a single chip, and including an FPU.
	open-encyclopedia.com /BiiN (918 words)

	CONK! Encyclopedia: Intel_i432 (Site not responding. Last check: 2007-09-07)
		The Intel iAPX 432 was Intel's first 32-bit microprocessor design, introduced in 1981 as a set of three integrated circuits.
		The iAPX 432 was intended to be Intel's major design for the 1980s, implementing many advanced multitasking and memory management features in hardware, which led them to refer to the design as the Micromainframe.
		Intel had spent considerable time, money and mindshare on the 432, had a skilled team devoted to it, and were loath to abandon it entirely after its failure in the marketplace.
	www.conk.com /search/encyclopedia.cgi?q=Intel_i432 (1822 words)

	Intel i960 - Encyclopedia Glossary Meaning Explanation Intel i960 (Site not responding. Last check: 2007-09-07)
		In spite of its success, Intel formally dropped i960 marketing in the late 1990s as a side effect of a lawsuit with DEC, in which Intel received the rights to produce the StrongARM CPU.
		To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, and the memory subsystem was made 33-bits wide -- for a 32-bit word and a "tag" bit to indicate protected memory.
		Intel attempted to bolster the i960 in the I/O device controller market with the I2O standard, but this had little success and the design work was eventually ended.
	www.encyclopedia-glossary.com /en/Intel-i960.html (852 words)

	School of Computer & Information Science - University of South Australia
		The Intel 8086 was based on the design of the 8080/8085 (source compatible with the 8080) with a similar register set, but was expanded to 16 bits.
		Intel bubble memory was on the market for a while, but faded away as better and cheaper memory technologies arrived.
		It was intended to be the main Intel microprocessor (some said the 80286 was envisioned as a step between the 8086 and the 432, others claim the 8086 was to be the bridge to the 432, rushed through design when the 432 was late and resulting in its many design problems).
	www.cis.unisa.edu.au /~cisbkg/cso/resources/cpu_history.html (16779 words)

	wikien.info: Main_Page (Site not responding. Last check: 2007-09-07)
		The i960 design was started as a response to the failure of Intel's i432 design of the early 1980s.
		The i432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory -- such as Ada and Lisp -- in hardware.
		By the mid-90's its price/performance ratio had fallen behind competing chips of more recent design, and Intel never produced a reduced power-consumption version that could be used in battery-powered systems.
	www.alanaditescili.net /index.php?title=Intel_i960 (803 words)

	Great Microprocessors of the Past and Present (Site not responding. Last check: 2007-09-07)
		Like the Nx586, AMD K5, and Intel's "Pentium Pro", the the third stage of the 10-stage 68060 pipeline translates the 680x0 instructions to a decoded RISC-like form (stored in a 16 entry buffer in stage four), and uses resource renaming to reorder instructions.
		Intel, with partner Hewlett-Packard, has begun development of a next generation 64-bit processor (compatible with the 80x86, probably also with an instruction translator or coprocessor), apparently based on Very Long Instruction Word technology, which may let the 80x86 architecture finally fade away.
		It was intended to be the main Intel microprocessor - the 80286 was envisioned as a step between the 8086 and the 432.
	www.inf.pucrs.br /~moraes/arquitetura/cpu_history.html (18038 words)

	Great Microprocessors of the Past and Present
		Texax Instruments followed the Intel 4004/4040 closely with the 4-bit TMS 1000, which was the first microprocessor to include enough RAM, and space for a program ROM, to allow it to operate without multiple external support chips.
		Like the National Semiconductor Swordfish, and later the Nx586, AMD K5, and Intel's "Pentium Pro", the the third stage of the 10-stage 68060 pipeline translates the 680x0 instructions to a decoded RISC-like form (stored in a 16 entry buffer in stage four), and uses resource renaming (with fourty rename registers) to reorder instructions.
		Intel also used BiCMOS in the Pentium and Pentium Pro to achieve clock rates competitive with CMOS load-store processors (the Pentium P55C (early 1997) version is a pure CMOS design).
	homepages.tesco.net /~scotsnet/o.f.carter/telcomps/cpu00.htm (16611 words)

	Read about Intel i860 at WorldVillage Encyclopedia. Research Intel i860 and learn about Intel i860 here! (Site not responding. Last check: 2007-09-07)
		The Intel i860 (also 80860, and code named N10) was a RISC
		Experience with the i860 influenced the MMX functionality later added to Intel's
		Intel i860 64-Bit Microprocessor (Data Sheet) (http://www.dvo.ru/bbc/hardware/mbc100/hard/i860.html) – From www.dvo.ru
	encyclopedia.worldvillage.com /s/b/Intel_i860 (846 words)

	Great Microprocessors of the Past and Present (Site not responding. Last check: 2007-09-07)
		Intel, with partner Hewlett-Packard, has begun development of a next generation 64-bit processor (code named Merced/Tahoe, compatible with the 80x86 in some versions, possibly with a hardware or software translater), apparently based on Very Long Instruction Word technology, which may let the 80x86 architecture finally fade away.
		Intel 80x86 processors, although much of the development of the superscalar core for a new AMD 29000 (including FPU designs from the 29050) was shared with the 'K5' (1995)
		Intel 80860, the 80960 was actually an overall better processor, and replaced the AMD 29K series as "the world's most popular embedded RISC" until 1996.
	www.history-of-cpu.euro.ru /history/cpu_history.html (15291 words)

	Who sank Itanic? \| The Register
		The project began at Intel in December 1991 and was announced as a partnership with Hewlett Packard - which had also been investigating VLIW designs - in 1994.
		The i432 was eventually sidelined in 1986, the year Intel's 80386 processor appeared.
		Not at all, says Intel, and the company can cite work on the multi-threaded multi-cored Tukwila (formerly Tanglewood) processor which is expected in two years' time, and which we exclusively revealed here.
	www.theregister.co.uk /2004/02/17/who_sank_itanic (1023 words)

	Great Microprocessors of the Past and Present (V 13.4.0)
		Largely obscured by the marketing hype surrounding the Intel 80860, the 80960 was actually an overall better processor.
		Like the Intel i860 (Intel's results from the initial joint project), PRISM could dispatch a single integer, or one integer and one floating point instruction per cycle, but in PRISM this was indicated by a bit in the integer instruction (similar to the TMS320C6x DSP) rather than a separate mode.
		In direct response to Intel's MMX instructions, AltiVec extensions were introduced with fourth generation (G4, September 1999) PowerPC CPUs from Motorola (IBM initially declined to support the extensions, until agreeing to become a second source of AltiVec CPUs for Apple Macintoshes).
	www.cpushack.net /CPU/cpu5.html (3434 words)

	Intel i960
		DEC, in which Intel received the rights to produce the StrongARM CPU.
		Myers tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and
		price/performance ratio had fallen behind competing chips of more recent design, and Intel never produced a reduced power-consumption version that could be used in battery-powered systems.
	en.efactory.pl /Intel_i960 (816 words)

	ENGLISH ENCYCLOPAEDIA - BiiN (Site not responding. Last check: 2007-09-07)
		BiiN was an outgrowth of Intel's iAPX 432 multiprocessor project, ancestor of iPSC and nCUBE.
		The central themes of the R&D effort were to be transparent multiprocessing and file distribution, dynamically switchable fault tolerance, and a high level of security.
		Unlike the i432, the 960 MC had fairly good performance, mostly as a side effect of dramatically reducing the complexity of the core instruction set, and including an FPU.
	encyclopaedic.net /english/bi/biin.html (983 words)

	Intel i860 - Encyclopedia Glossary Meaning Explanation Intel i860 (Site not responding. Last check: 2007-09-07)
		Intel i860 - Encyclopedia Glossary Meaning Explanation Intel i860.
		Here you will find more informations about Intel i860.
		Confusingly, the i860 name has now been re-used for a motherboard control chipset for Intel Xeon (high-end Pentium) systems.
	www.encyclopedia-glossary.com /en/Intel-i860.html (968 words)

	Intel i960 \| TutorGig.co.uk Encyclopedia (Site not responding. Last check: 2007-09-07)
		The i960 design was started as a response to the failure of Intel's iAPX 432 design of the early 1980s.
		The iAPX 432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory -- such as Ada and Lisp -- in hardware.
		To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, only implemented in full in the 'i960MX', and the memory subsystem was made 33-bits wide -- for a 32-bit word and a "tag" bit to indicate protected memory.
	www.tutorgig.co.uk /ed/Intel_i960 (898 words)

	Intel i860 - ArtPolitic Encyclopedia of Politics : Information Portal
		The i860 never became very popular, and is no longer made.
		From this description, it should be obvious where Intel's later MMX functionality came from.
		The chip was released in two versions, the basic XR, and the XP (code name N11).
	www.artpolitic.org /infopedia/in/Intel_i860.html (662 words)

	i432 (Site not responding. Last check: 2007-09-07)
		I bought an Intel 200 series expansion box, mainly because it had the two card set for the Intel double density.
		(Intel's double density is not compatible with others.) There was another board in the chassis that I didn't even look at much.
		I just assumed it was some ICE board without the dongle so I didn't give it much thought.
	www.classiccmp.org /pipermail/cctalk/2002-July/003636.html (148 words)

	Intel i432
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		It had on-chip support for handling the data structures common to object-oriented programming and multitasking, allowing modern operating systems to be implemented on it with far less code -- the CPU would do much of the work intenally instead.
		The two-chip implementation of the GDP limited it to speed of the motherboard's electical wiring, although this is a minor isse.
	www.sciencedaily.com /encyclopedia/intel_i432 (745 words)

	Great Microprocessors of the Past and Present
		IBM had been developing hardware to translate Pentium instructions for the PowerPC in a similar manner as part of the PowerPC 615 CPU (able to switch between instruction 80x86, 32-bit and 64-bit PowerPC instruction sets in five cycles (to drain the execution pipeline)), but the project was killed after significant development for marketing reasons.
		graphics extensions without waiting for Intel's 3D MMX extensions (expected to be introduced with the "Katami" version, including eight new 128 bit registers (like the PowerPC AltiVec registers), and referred to as the "Katami New Instructions" (KNI)).
		It is expected to be a variable length instruction group (VLIG or what HP/Intel call EPIC (Explicit Parallel Instruction Computing)) with instruction dependencies grouped from 1 to 9+.
	www.engj.ulst.ac.uk /sidk/files/cpu_hi.html (16577 words)

	Great Microprocessors of the Past and Present
		Texas Instruments followed the Intel 4004/4040 closely with the 4-bit TMS 1000, which was the first microprocessor to include enough RAM, and space for a program ROM, to allow it to operate without multiple external support chips.
		Intel, with partner Hewlett-Packard, has begun development of a next generation 64-bit processor architecture called IA-64 (the 80x86 design was renamed IA-32).
		It is expected to translate 80x86 instructions into VLIW instructions (or directly to decoded instructions) the same way that Intel P6 and AMD K5/K6/K7 CPUs do, but with a larger number of instructions issued using the VLIW design, it should be faster.
	www.geocities.com /rabeeljaved/cpuhis.html (15799 words)

	[No title] (Site not responding. Last check: 2007-09-07)
		graphics extensions without waiting for Intel's 3D MMX extensions (expected to be introduced with the "Katami" version, including eight new 128 bit registers (like the PowerPC AltiVec registers), and initially referred to as the "Katami New Instructions" (KNI), but officially called SSE).
		It is expected to be a variable length instruction group (or what HP/Intel call EPIC (Explicit Parallel Instruction Computing)) with instruction dependencies grouped from 1 to 9+.
		Rumour has it that delays and performance limits, but probably more SGI's financial problems, meant that the R10000 and derivatives (R12K and R14K) were the end of the high performance line for the MIPS architecture.
	www.pfmb.uni-mb.si /marjan/burks1/pcinfo/hardware/cpu.htm (15872 words)

	MacOS on X86? (Site not responding. Last check: 2007-09-07)
		They've created quite a >> few non-x86 chips in the past, and are doing it to this day, and none >> of those have been a success.
		There was quite a bit of hoo-ha when the i860 was introduced, and putting a 64 bit (at least, according to Intel it was 64 bit) processor in a laser printer seems to be a bit of a waste.
		The page also mentions the i432, another Intel failure.
	www.ampfea.org /pipermail/music-bar/2005-June/111724.html (224 words)

	Great Microprocessors of the Past and Present
		Like the National Semiconductor Swordfish, and later the Nx586, AMD K5, and Intel's "Pentium Pro", the the third stage of the 10-stage 68060 pipeline translates the 680x0 instructions to a decoded RISC-like form (stored in a 16 entry buffer in stage four).
		The K7 it replaces the Intel-compatible bus of the K6 with the high speed Alpha EV6 bus because Intel decided to prevent competitors from using its own higher speed bus designs (Dirk Meyer was director of engineering for the K7, as well as co-architect of the Alpha 21064 and 21264).
		The design also pays attention to supporting common code sequences - for example, loads occur earlier in the pipeline than stores, allowing load-alu-store sequences to be more efficient.
	www.uib.es /c-calculo/scimgs/fc/tc4/html/cpu_history.html (16479 words)

	Great Microprocessors of the Past and Present
		So why did IBM chose the 8-bit 8088 (1979) version of the 8086 for the IBM 5150 PC (1981) when most of the alternatives were so much better?
		In direct response to Intel's MMX instructions, AltiVec extensions are planned for fourth (G4) generation PowerPC CPUs from Motorola (but not IBM).
		It's an interesting tradeoff, considering that a highly parallel 71.5 MHz POWER2 managed to be faster than a 200MHz DEC Alpha 21064 of the same generation.
	www.unixhub.com /docs/misc/cpu.html (16707 words)

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