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Topic: JHDL

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	JHDL - Wikipedia, the free encyclopedia
		JHDL (Java Hardware Description Language) is a low level hardware description language, focused primarily on building circuits via an Object Oriented approach that bundles collections of gates into Java objects.
		JHDL was developed at BYU in the Configurable Computing Laboratory.
		The integrated JHDL Workbench environment is designed to allow developers to graphically test and trace their circuit designs.
	en.wikipedia.org /wiki/JHDL (220 words)

	VTBYU Project (Site not responding. Last check: 2007-09-20)
		JHDL is a language developed with the intent of elegantly embodying the run-time reconfiguration paradigm in a commonly used (familiar) programming environment.
		The primary distinction of JHDL and indeed the primary goal of this project is the creation of a single integrated API that allows the designer to express circuit organizations that dynamically change over time.
		In addition to continuing experimentation with JHDL for CCM applications, two areas have been identified for further work in JHDL: netlisting, to allow JHDL to function as a complete structural design tool, and behavioral synthesis, to allow circuits to be expressed at a higher level.
	www.ee.vt.edu /~ccm/vtbyu/vtbyujhdl.html (937 words)

	JHDL: FPGA CAD TOOLS -- Brigham Young University (Site not responding. Last check: 2007-09-20)
		JHDL is a set of FPGA CAD tools developed at Brigham Young University's Configurable Computing Laboratory that allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist and interface for bit-stream synthesis, and so forth.
		The latest version of JHDL, release 0.3.45, is now available for download.
		JHDL was last updated on 11 May 2006.
	www.jhdl.org (121 words)

	SOCcentral: BYU JHDL, open source FPGA CAD tools (BYU Configurable Computing Laboratory 124)
		JHDL is a method of describing (programmatically, in Java) the components and connections in a digital logic circuit.
		Because JHDL relies on a high-level language, it is easy to integrate the "hardware part" of the application with the "software part." The user models and controls his circuit with Java classes, which can naturally interface with GUI objects, file or console I/O routines, and so forth.
		JHDL has displaced all other CAD tools and is used extensively to develop high-performance applications in automated target recognition, sonar beamforming, and other applications.
	www.soccentral.com /results.asp?EntryID=124 (1518 words)

	JHDL - JGCWiki
		JHDL (originally expanding to Java Hardware Description Language, but now expanding to Just-another Hardware Description Language) is a low level HDL designed to allow hardware designers to develop hardware in the Java Language.
		The advantage of its low level design is that it is capable of being used in areas where behavioral languages such as VHDL make the physical circuit layout difficult.
		JHDL tends to make up for such failings by allowing a more Object Oriented approach to building a circuit.
	jgcwiki.datadino.com /jgcwiki/index.php?title=JHDL (119 words)

	Re: gEDA-user: fpga
		As others have mentioned, JHDL is not a complete solution; you still need the "free beer" Xilinx tools (currently, I use the Windows version of Webpack ISE and run it under Wine).
		JHDL is used in the "front end" of the project, where you might otherwise use VHDL, Verilog, or schematic capture.
		JHDL is a Java library for generating EDIF netlists.
	www.mail-archive.com /geda-user@seul.org/msg06708.html (298 words)

	Building JHDL
		JHDL is built (compiled, etc.) using the Ant build system.
		If you are building JHDL on a computer other than the lab's Linux machines, you will have to obtain and install Ant on your own.
		If you are attempting to build JHDL on some other system, you should try to set up the system as similarly as you can.
	splish.ee.byu.edu /lab/devhelps/jhdl_build.html (2792 words)

	EETimes.com - Lab to offer open-source Java-based FPGA tool
		JHDL provides an alternative to both conventional HDLs and C/C++ design methodologies pursued by commercial EDA vendors.
		A key JHDL feature is a user interface that serves both simulation and hardware execution.
		As it exists today, JHDL includes a library of data path modules, a graphical debugging tool that supports both simulation and hardware execution, a schematic generator, an EDIF 2.0 netlist class, and EDIF parser, simulation models for Annapolis Microsystems Inc.'s WildForce platform, and a state-machine generator.
	www.eetimes.com /story/OEG20010831S0086 (1261 words)

	Final Report (Site not responding. Last check: 2007-09-20)
		Through the flexibility of JHDL, an environment was created that will allow an audio engineer to customize the filtering behavior of the WildForce board while not being required to understand the details of the hardware language that is being used.
		I feel that the fact that JHDL is built from the standard Java language should be the focus of teaching JHDL.
		It is my opinion that the exploration of JHDL is going to require more and more Java expertise as we move from just implementing static circuits to implementing circuits that react.
	www.ee.vt.edu /~burnett/final_report.html (795 words)

	Slashdot \| Anyone Using JHDL for Programmable Logic?
		JHDL is supposedly good, but lacks in synth dept.
		JHDL is fairly sophisticated, and it is an impressive tool given that it is mostly a student-developed application.
		JHDL seems to be a Java based methodology for creating structural circuits which also happen to be simulatable using the Java environment.
	slashdot.org /developers/02/01/16/219258.shtml (8496 words)

	FPGA CAD Tool Directory (Site not responding. Last check: 2007-09-20)
		JHDL can be a stand-alone CAD Tool as well, able to go straight from design in a.java file to simulation & verification to techmapping and writing the design to a.bit file, ready to download to an FPGA part.
		JHDL support is also ongoing at Brigham Young University's Configurable Computing Lab.
		RHDL an 'Agile HDL', based on an object orientated language like JHDL, except at a higher level due to the typelessness of Ruby, allows the design process to be more high level than conventional object orientated langues.
	www.xaxxeon.com /fpga/index.html (433 words)

	A CAD Suite for High-Performance FPGA Design
		This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high-performance configurable-computing applications.
		JHDL provides a unified design environment where a single, user interface can be used for both simulation and execution.This allows the designer to request either simulation or execution (or a mixture of the two) using the exact same commands for both.
		JHDL is currently being used to design several complex applications in image processing and signal processing.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/fccm/1999/0375/00/0375toc.xml&DOI=10.1109/FPGA.1999.803663 (227 words)

	[No title]
		* * JHDL actors that are derived from this class need to * create their JHDL circuit and Wires in the * initialize method.
		System.gc(); } /** * setInputs() is a method used to set the inputs of the JHDL * circuit from the Ptolemy tokens.
		This will be called before * the clock() method to insure the inputs for the JHDL clock call * are set.
	www.ee.byu.edu /beta/faculty/wirthlin/projects/ptjhdl/SDFJHDLActor.java (701 words)

	[No title] (Site not responding. Last check: 2007-09-20)
		JHDL is a structural design tool written in Java for high-performance FPGA designs developed at Brigham Young University.
		JHDL circuits are created by writing Java class files that extend the base classes found in the JHDL distribution.
		An overview of JHDL can be found on the JHDL web site and in a paper on JHDL published at FCCM '99.
	www.ee.byu.edu /faculty/wirthlin/projects/ptjhdl.html (310 words)

	Citations: Using General-Purpose Programming Languages for FPGA Design - Hutchings, Nelson (ResearchIndex) (Site not responding. Last check: 2007-09-20)
		While JHDL has been used primarily as a stand alone design tool, it o#ers a number of tools and aids for describing, evaluating, and....
		JHDL JHDL is a open source design environment developed at BYU used for creating high performance FPGA designs
		JHDL was developed by the Configurable Computing Laboratory at Brigham Young University to facilitate describing circuits for reconfigurable computing platforms.
	citeseer.ist.psu.edu /context/1799585/555261 (856 words)

	[No title] (Site not responding. Last check: 2007-09-20)
		This is the approach we took for JHDL.
		In our case, we created a new domain for JHDL and were able to interface our simulator (a statically scheduled logic simulator) to other domains in Ptolemy.
		>>> >>>http://www.jhdl.org/ says: >>>"JHDL is a set of FPGA CAD tools developed at Brigham Young >>>University's Configurable Computing Laboratory that allows the user >>>to design the structure and layout of a circuit, debug the circuit in >>>simulation, netlist and interface for bit-stream synthesis, and so >>>forth.
	ptolemy.eecs.berkeley.edu /mailing-lists/split/0410/Re:_[ptII]_VHDL__JHDL13 (838 words)

	JHDL Download
		The copyrights and other intellectual property of BYU in and to the JHDL Software are referred to herein as the "BYU Intellectual Property." As this term is used in this Agreement, "BYU Intellectual Property" does not include any other copyrights or intellectual property of BYU.
		The U.S. Government or any of its agencies, departments, ministries, military or entities (any or all of the foregoing hereafter referred to as "Government") has limited rights to use, modify, reproduce, release, perform, display, disclose or further develop this Software, in whole or in part, for Government purposes and/or within the Government.
		This Agreement sets forth the entire agreement between the parties concerning the subject matter of this Agreement and may be amended only in a writing signed by both parties.
	www.jhdl.org /download.html (888 words)

	Sprout - April 2003
		JHDL is a Java based Hardware Description Language created at the Configurable Computing Laboratory of Brigham Young University.
		With JHDL you create a circuit structure using Java object classes.
		JHDL eliminates the need for a "domain specific" programming language and development environment such as VHDL.
	www.netbeans.org /community/news/newsletter/sprout/2003-05-15.html (1445 words)

	A CAD Suite for High-Performance FPGA Design - Hutchings, Bellows, Hawkins, Hemmert, Nelson, Rytting (ResearchIndex) (Site not responding. Last check: 2007-09-20)
		Abstract: This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high-performance configurable-computing applications.
		The basis of this tool suite is JHDL [1], a design tool originally conceived as a way to experiment with Run-Time Reconfigured (RTR) designs.
		However, what began as a limited experiment to model RTR designs with Java has evolved into a comprehensive suite of design tools and verification aids, with these tools being...
	citeseer.ist.psu.edu /hutchings99cad.html (466 words)

	OpenCollector Database (Site not responding. Last check: 2007-09-20)
		JHDL is based on Java: a JHDL design consists of a structural description of a circuit, which can be compiled to execute on the Java JAB simulator.
		Circuits may also be created using utilities such as the finite-state machine generator, which works from tabular input.
		JHDL also includes features for FPGA mapping and placement (using annotation hints), and can produce EDIF netlists suitable for exporting to FPGA backend tools.
	opencollector.org /get_details.php?uid=447&src=summary (80 words)

	FPGA FAQ comp.arch.fpga archives - messages from 45900
		What i mean is, is there a tool (like Xilinx > has) you know of I can use to generate JHDL from the states I would > enter.
		JHDL has a built in FSM generator; you give it the states and it spits out state machines.
		It described pretty well in the JHDL users manual: http://www.jhdl.org/docs/docs/usersManual/fsm.html If you have more questions, try the to JHDL mailing list (click on "mailing list" from www.jhdl.org) -- it's read directly by JHDL developers and they are more than happy to answer any and all questions you may have.
	www.fpga-faq.org /archives/45900.html (4221 words)

	WPI Computer Science - Support for Runtime Execution in Reconfigurable Hardware (Site not responding. Last check: 2007-09-20)
		Tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware will be presented.
		JHDL is used to describe the reconfigurable hardware, and JavaPorts to handle the communications between nodes in the network.
		The heterogeneous resources are handled by interposing a communication layer between the application and the hardware.
	www.cs.wpi.edu /News/Colloquium/20001/20010330.html (173 words)

	FPGA Reliability Studies - Power Studies
		A JHDL program can be used to determine the activity rates of the nets from a given design, and then use that information to create an XML file that is readable by XPower.
		Creating XML files using JHDL successfully assigns activity rates to every net of a design (and acheive an 'accurate' confidence level in XPower), however JHDL is unable to simulate transient signals.
		Without being able to simulate transient signals, the activity rates produced by JHDL will be too low resulting in inaccurate XPower power consumption reports.
	reliability.ee.byu.edu /power/xpower.htm (623 words)

	C as a Hardware Design Language
		In the last few years there has been a lot of work on tools for VLSI layout and timing analysis.
		A similar multiplier is also discussed in Keshab Parthi's book on DSP design.
		JHDL® is a set of FPGA CAD tools developed at Brigham Young University's Configurable Computing Laboratory that allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist and interface with back-end tools for synthesis, and so forth.
	www.bearcave.com /cae/chdl (2382 words)

	EDIF -> Map & Place -> EDIF ?
		feature of JHDL, which is the ability to parse and translate EDIF into a
		this, the JHDL system has to know the bounding boxes for a and b.
		be bothered to place manually, but still use the JHDL placement stuff.
	www.castalk.com /ntopic137.html (2996 words)

	Computer Science and Engineering Department, Washington University in St. Louis - Colloquia (Site not responding. Last check: 2007-09-20)
		I will also discuss current challenges for tools used to program configurable systems and will present JHDL, a Java-based CAD environment that interfaces directly with configurable computing hardware and allows designers to develop and debug applications directly on configurable hardware.
		Finally, I will discuss a promising, new application of configurable computing that can significantly enhance network security and discuss how it was organized with JHDL.
		Brad Hutchings received the Ph.D. degree in Computer Science from the University of Utah in 1992.
	www.cse.seas.wustl.edu /ColloquiaEvent.asp?77 (316 words)

	Re: gEDA-user: fpga
		On Tue, Nov 01, 2005 at 07:07:05PM -0600, David Hart wrote: > On Tue, 2005-11-01 at 16:52 -0500, Darrell Harmon wrote: > > Though not a GNU project, the JHDL Project is an OpenSource project.
		> > > > Darrell Harmon > > http://dlharmon.com > -- > David Hart <[EMAIL PROTECTED]> > It appears that JHDL produces EDIF output which must be converted to a bitstream by Xilinx tools.
		I believe Icarus Verilog has similar support for some Xilinx parts, and I plan to take a look at that someday.
	www.mail-archive.com /geda-user@seul.org/msg06598.html (203 words)

	BYU FPGA Lab: JHDL Release Process
		Update the JHDL webpage to reflect the latest version *
		(modify /ka1/WWW/swish-e/index.it: 1- Change the version number on the right-handed short-cut menu (under download JHDL) 2- Change the "announcement" to read "JAVA JHDL Version 0.3.x Released", change the date of the announcement as well.
		Also be sure to test the source code release by pretending to be a new JHDL user and trying to compile it
	splish.ee.byu.edu /lab/release_process.html (533 words)

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