Logic redundancy - Factbites

Logic redundancy - Factbites
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Topic: Logic redundancy

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	Vertical encoding - Computing Reference - eLook.org
		An instruction set where a field (a bit or group of bits) of the instruction word is decoded (either by hard-wired logic or microcode) to generate signals to control the functional units, as opposed to horizontal encoding where the instruction word bits are used as the control signals directly.
		With vertical encoding, which combinations of signals and operations are possible is dictated by the decoding logic; the instruction field can only select one of these preprogrammed combinations.
		An instruction set may use a mixture of horizontal and vertical encoding within each instruction.
	www.elook.org /computing/vertical-encoding.htm

	Boolean Algebra in terms of the exclusive-OR operator - 2
		This concludes the demonstration that exclusive-OR logic is both a complete Boolean algebra in its own right and has all the graphical and algebraic simplification methods necessary for working with this algebra at least with paper and pencil.
		However, in the algebraic approach to simplification you may not know in advance whether to use a particular redundancy or not prior to performing the simplification process.
		As pointed out in the discussion of Figure 4, in the first part of this paper (Figure 9 in the "New Logic" article), simplification by inspection of a K-map of functions of more than three variables may not be immediately obvious.
	users.senet.com.au /~dwsmith/concept2.htm

	CRN LSI Logic Channel Effort Foreshadows
		LSI Logic is also preparing a version of MyStorage with dynamic multi-pathing capabilities that allow fail-over to a second HBA should the primary adapter fail, adding redundancy to low-cost SANs, Looby said.
		MyStorage will be bundled with LSI Logic HBAs, drivers and cables in kits for distribution when the software comes out of beta, he said.
		LSI Logic today has about 300 partners, he said.
	www.crn.com /sections/breakingnews/breakingnews.jhtml?articleId=18841552&_requestid=12443 (850 words)

	Natural Language Laboratory: Theoretical Work
		The transformations are done using Montague's (Thomason, 1974) style of coupling syntactic and semantic processing but not his use of an intensional logic the intermediate representation used is a lambda-categorial language (a typed predicate calculus language with a lambda-operator).
		Non-literal language, of which metaphor and metonymy are types, includes phenomena whose meaning cannot be obtained by direct composition of their constituent words (see Fass et al., 1991, 1992a).
		The classification of natural language generation systems is based on a number of dimensions such as objectives, stages of evolution and approaches to the modelling of linguistic knowledge.
	www.cs.sfu.ca /fas-info/cs/research/groups/NLL/2.html (3999 words)

	resume_text.txt
		EDUCATION Masters of Science (M.S.) GPA: 3.6/4.0 May’03 Electrical and Computer Engineering Rutgers, The State University of New Jersey, New Brunswick, NJ Bachelors of Engineering (B.E.) GPA: 3.85/4.0 (TOP 5%) June’01 Electrical Engineering Major: Instrumentation and Control Gujarat University, India M.S. Redundancy Identification in Logic Circuits, using Implication Graph and Stem Unobservability Theorems.
		Survey of, Redundancy Identification using Transitive Closure, Techniques, and new proposal Surveyed two research thesis, and two papers based on these thesis.
		My undergraduate study was focused on concepts including both electrical engineering and computer science to provide technical proficiency needed for the professional practice of electrical and computer engineering, included the design and application of electrical, electronics design, components and systems.
	www.caip.rutgers.edu /~mehta/resume_text.txt (878 words)

	Logic grammars and XML Schema
		The regularities of schema processing would be more obvious, and much of this redundancy could be eliminated, if we represented simple types, complex types, attributes, and elements not as sets of Prolog rules but as structured data, which is passed to parsing rules as a parameter.
		Move up one level of abstraction: model the schema for schemas as a logic grammar; use it to parse schema documents and generate the appropriate schema components.
		This schema will serve admirably to illustrate the translation of schemas to logic grammars.
	www.mulberrytech.com /Extreme/Proceedings/html/2003/Sperberg-McQueen01/EML2003Sperberg-McQueen01.html (8389 words)

	ARTICLES by Jim Hurford
		2003 (with Catriona Tullo) ``Modelling Zipfian Distributions in Language'' (PDF file), paper presented at the Language Evolution and Computation Workshop/Course at the 15th European Summer School on Logic Language and Information, Vienna, August 2003.
		1989 ``Biological Evolution of the Saussurean Sign as a Component of the Language Acquisition Device'' (PDF), Lingua, 77,2:187-222.
		In Simulating the Evolution of Language, edited by Domenico Parisi and Angelo Cangelosi, Springer Verlag, Berlin.
	www.ling.ed.ac.uk /~jim/articles.html (1114 words)

	Lehrstuhl für Anlagensteuerungstechnik - Specialisation course: Logic Control
		Basic Mathematics for logic control: Boolean algebra, Boolean Functions and their Minimization
		Automation of technical processes, Instrumentation, Characteristics of logic controllers, Examples and Objectives
		Hierarchy of control functions, Distributed control systems, Redundancy and safety
	astwww.bci.uni-dortmund.de /en/content/lehre/evertiefungsveranst/elcd.html (162 words)

	Object Level Fault Tolerance for CORBA-based Distributed Computing
		Logical topology describes how processes (i.e., logical nodes) are organized to cooperate with each other.
		Redundancy, the key to achieving fault tolerance in distributed systems, is often achieved in a CORBA-based distributed systems using replica creation and management services distributed through an ORB bus-based topology.
		In this case, process ‘a’ on processor ‘A’ has a logical communications path to process ‘d’ on processor ‘D’ which transverses processor ‘C’.
	dantanner.tripod.com /FT.htm (1857 words)

	\Large \bf Myriad: Cost-effective Disaster Tolerance
		However, mirroring is expensive: the amount of physical data is twice the amount of logical data (often referred to as ``100% space overhead''), so one must purchase and administer twice as much storage as for a basic (disaster-vulnerable) system.
		The previous section argued that, contrary to common supposition, the cost of disaster tolerance is highly dependent on the storage overhead of the cross-site data redundancy scheme.
		When a client writes to a (logical) data block, we create a new outstanding data version by writing the data into a free physical block and logging the outstanding version with the new physical address.
	www.usenix.org /events/fast02/full_papers/chang/chang_html (9047 words)

	Vertical encoding - Computing Reference - eLook.org
		With vertical encoding, which combinations of signals and operations are possible is dictated by the decoding logic; the instruction field can only select one of these preprogrammed combinations.
		An instruction set may use a mixture of horizontal and vertical encoding within each instruction.
		This has the advantage that many control signals can be generated based on only a few instruction word bits and only valid combinations of control signals can be generated, e.g.
	www.elook.org /computing/vertical-encoding.htm (9047 words)

	Cyclic Redundancy Check - Dev Shed
		Cyclic Redundancy Check Security and Cryptography forum discussing issues relating to coding, server applications, network protection, data protection, firewalls, ciphers and the like.
		Discuss Cyclic Redundancy Check in the Security and Cryptography forum on Dev Shed.
		This is what my logic tells me: You should be able to say, multiply the given file by its Public Key (PGP Block) to decrypt it, granted, but also to verify its integrity, or just to verify its integrity, capisci?
	forums.devshed.com /security-and-cryptography-17/cyclic-redundancy-check-197814.html (284 words)

	VX STEP Utility:
		This reveals two flaws in the documentation that need to be addressed: Accuracy and Redundancy.
		#n=TOLERANCE_ZONE (/* shape_aspect / name / label /, description / text /, of_shape / product_definition_shape /, product_definitional / LOGICAL / / tolerance_zone /,defining_tolerance / SET [1:] OF geometric_tolerance /, form / tolerance_zone_form */);
	www.vx.com /cgi-bin/STEP/stp_grf.cgi?ntxt=760 (132 words)

	ACRONYM.txt
		Redundant Arrays of Inexpensive Disks RAIS Redundant Arrays of Inexpensive Systems RALU Register Arithmetic Logic Unit RAM "radar absorbing material
		Longitudinal Redundancy Check LRL Least Recently Loaded LRM Language Reference Manual
		Cyberspatial reality advancement movement CRBR Clinch River Breeder Reactor Project CRC Cyclic Redundancy Check CRD Capacitor-resistor diode CRDA Control rod drop accident CREN Computer Research Education Network
	www.chris.slade.btinternet.co.uk /ACRONYM.txt (10222 words)

	IEEE Transactions on Computers,January 1989 (Vol. 38, No. 1)
		Index Terms- system-level design; triple modular redundancy; gate-level design; N-tuple modular redundancy; redundant logic design; quadded logic; error masking; fault-tolerant design; redundancy; fault-tolerant system design; interwoven logics; mathematical block theory; redundant design; fault tolerant computing; logic design; redundancy.
	doi.ieeecs.org /10.1109/12.8727 (10222 words)

	Scott Smolka's Recent Publications
		The principal merits of this extension are that XSB terminates on programs having finite models, avoids redundant subcomputations, and computes the well-founded model of normal logic programs.
		In this paper, we demonstrate the feasibility of using XSB as a programmable We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers.
		We have applied our redundancy checker to a number of previously published case studies, and found instances of redundancy that have gone unnoticed till now.
	www.cs.sunysb.edu /~sas/papers (10222 words)

	publications
		Nuno Fonseca, Vítor Costa, Fernando Silva, Rui Camacho, ``Redundancy in Inductive Logic Programming'' na 14th International Conference on Inductive Logic Programming (ILP 2004), eds.
		Nuno Fonseca, Ricardo Rocha, Rui Camacho, Fernando Silva (2003): ``Efficient Data Structures for Inductive Logic Programming'' in 13th International Conference on Inductive Logic Programming (ILP 2003), eds.
		Nuno Fonseca, Rui Camacho, e Fernando Silva: ``A parallel ILP algorithm that incorporates incremental batch learning'', na Workshop on Parallel and Distributed Computing for Machine Learning, na ECML/PKDD-2003 14th European Conference on Machine Learning, 22-26 September, Dubrovnic, Croacia, 2003
	paginas.fe.up.pt /~rcamacho/html/publications.html (1196 words)

	Cornell University
		The redundancy of this code is a little under 50% (15 bits/31 bit block), while the redundancy of the (31, 11) 5-error correcting code (the next allowable code which has a degree 20 generator polynomial) is much worse (20 bits/31 bit block).
		After this (rather lengthy) mathematical discussion on algebraic block codes, we can now describe some of the reasons and logic behind our code selection.
		Implementing a (31, 16) BCH code on the Mega32 microcontroller; Design Logic:
	instruct1.cit.cornell.edu /Courses/ee476/FinalProjects/s2004/abk26 (2362 words)

	EETimes.com - Mosys, Iroc target IC error protection
		Iroc maintains that the technique it uses to combat errors in logic can be implemented without the speed degradation caused by building in time-redundancy circuitry, a way of duplicating information and observing the outputs of a circuit at different times to ensure that the data is reliable.
		To combat errors in logic, Iroc has come up with another special cell to catch and fix faults before they make their way to the registers, at which point they can cause failures.
		For memory, the company offers a suite of IP that includes a code generator, code bits and error logic that is said to keep errors to zero.
	www.eetimes.com /story/OEG20020206S0026 (1105 words)

	Библиотека RIN.ru - Измайлова А. - The Theory of Truth in the Writings of William James
		Peirce described pragmatism as a "logical doctrine" and a "theory of logical analysis", his pragmatism was presented as a methodological rule, considering it a part of logic.
		There are five main `theories of truth`: the correspondence theory, the coherence theory, and the pragmatic, redundancy and semantic theories.
		He tries to force that James either remains immanent in human experience or commits himself to a doctrine, which refutes itself, or permits his analysis of how we arrive at judgments of error to be supplemented with an account of "the logical conditions" of error.
	lib.rin.ru /doc/i/198465p.html (1072 words)

	pub.bib
		A novel representation of clauses in minimal logic such that the representation of resolution steps is linear in the size of the premisses.
		- A novel representation of clauses in minimal logic such that the lambda-representation of resolution proofs is linear in the size of the premises.
		It is surprising to see that one does not need any sophisticated simplification and redundancy elimination method to make superposition terminate on the class of clauses that is obtained from the clausification of guarded formulas.
	www.mpi-sb.mpg.de /~nivelle/publications/pub.bib (1072 words)

	FreeLists / foxboro / Re: [foxboro] Annuciator keyboard horn silence button
		By entries in this file, one can point the alarm horn function to something like a CALC or LOGIC block, and add additional logic there.
		If the system has more than one workstation, the same 'horn.cfg' is put in each WP, and redundancy is achieved.
		The horn is silenced in three cases; - when the Horn Silence key is pressed, - when the Alarm button on DM or FoxView is picked (calling up the Alarm Display) - when any display key is hit on the annunciator keyboard.
	www.freelists.org /archives/foxboro/08-2002/msg00079.html (1072 words)

	DBLP: Nuno Fonseca
		Nuno Fonseca, Vítor Santos Costa, Fernando M. Silva, Rui Camacho: On Avoiding Redundancy in Inductive Logic Programming.
		Nuno Fonseca, Ricardo Rocha, Rui Camacho, Fernando M. Silva: Efficient Data Structures for Inductive Logic Programming.
		Nuno Fonseca, Vítor Santos Costa, Fernando M. Silva, Rui Camacho: Experimental Evaluation of a Caching Technique for ILP.
	www.informatik.uni-trier.de /~ley/db/indices/a-tree/f/Fonseca:Nuno.html (143 words)

	Patent 4312068: Parallel generation of serial cyclic redundancy check
		On step number 1, the old residue is exclusive OR'ed bit by bit by the arithmetic and logic unit ALU with the new data in the arithmetic and logic unit ALU 422 and the result is temporarily stored in the accumulator.
		Finally, step number 9 stores the result of the accumulator in a predetermined position in scratchpad memory as a residue and is the cyclic redundant check character for the word just received.
		Thus the same apparatus in the device that generates the cyclic redundant check character is also used to check a unit of data received as a result of a read operation.
	www.freepatentsonline.com /4312068.html (143 words)

	Altera Corporation- Quarterly Earnings
		The Stratix II family features an entirely new logic structure and is the only programmable logic device to use an advanced 90-nanometer process with high performance, low-k dielectric materials.
		Stratix II, like Altera's previous high-density FPGA families, also will benefit from the use of Altera's patented redundancy technology.
		The Cyclone II family is the second line of Altera FPGAs to be built on TSMC's production-proven 90-nanometer, low-k process.
	phx.corporate-ir.net /phoenix.zhtml?c=83265&p=irol-newsArticle&t=Regular&id=594606& (1254 words)

	Fall 99, CSE 520: Lectures
		The correspondence with intuitionistic validity comes from the observation that the rules of the type system, when we consider only the type part, are exactly the rules of the (implicational fragment of) intuitionistic logic.
		The elimination of such redundancy transforms the proof into a new proof, in a way which corresponds to making a step of beta-reduction.
		Beta redexes correspond to the presence of a redundancy in the proof, namely the application of a ->introduction rule followed by the application of a ->elimination rule.
	www.cse.psu.edu /~catuscia/teaching/cg520/99Fall/lecture_notes/L11and12.html (1254 words)

	User:Waveguy/brain dump - Wikipedia, the free encyclopedia
		Low frequency, LNA, Laser, Lead-lag effect, Light-dependent resistor, Light-emitting diode, Linear feedback shift register, Linear regulator, Logic gate, Logic, Low noise amplifier, Launch angle, Launch numerical aperture, Leaky mode, Limiting, Line code, Lip synchronization, Loading characteristic, Loading coil, Loading, Local battery, Log-periodic antenna, Long-haul communications, Long-term stability, Longitudinal redundancy check, Loop gain, Loop-back, Low-performance equipment,
		OLTP, Ohm's law, Open spectrum, Operational amplifier, Optical spectrum, Off-hook, Off-line, On-hook, On-line, One-way trunk, Operating time, Operational service period, Optical density, Optical path length, Optoelectronic, Output rating, Outside plant, Overflow, Overhead information, Overmodulation, Override, Overshoot, Optical fiber, Orthogonal frequency division modulation
		Quadrature, Quality assurance, Quality control, Queuing delay, Q-switching, QRP operation, Q code, Quadrature amplitude modulation
	en.wikipedia.org /wiki/User:Waveguy/brain_dump (382 words)

	United States Patent: 6,744,094
		In another embodiment, an array of floating gate transistors is a field programmable logic array with the source regions of a common column electrically interconnected, the drain regions of a common row electrically interconnected, and the control gates interconnected along the direction of the columns.
		One advantage of the single control gate 335 is redundancy in the selection of an output, but one drawback is the loss of circuit density because of the duplication.
		If there are no electrons stored on the floating gate 202, the floating gate transistor 200 conducts between its source region 310 and drain region 315, decreasing the voltage of the corresponding output line toward the voltage of the source region 310, e.g., toward a "low" binary logic level voltage of approximately zero volt.
	web.engr.oregonstate.edu /~flf/6744094.html (10285 words)

	Encyclopedia: Truth
		Truth tables are a type of mathematical table used in logic to determine whether an expression is true or whether an argument is valid.
		The Redundancy theory of truth is a philosophical theory about the way in which the predicate is true functions in such sentences as Snow is white is true.
		For example, the redundancy theory of truth holds that to assert that a statement is true is just to assert the statement itself.
	www.nationmaster.com /encyclopedia/Truth (5118 words)

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