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Topic: Logic simulators

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	Logic-level Simulators (Site not responding. Last check: 2007-10-24)
		Logic-level simulators attempt to remedy the computationally intensive nature of circuit-level simulators by raising the level of abstraction to the domain of switches and logic components.
		During the simulation itself, equations governing the behaviour of the circuit are greatly approximated, thereby increasing the speed at which the simulator operates.
		Such simulators are commonly referred to as mixed-mode simulators [8].
	www.cs.mun.ca /~donald/msc/node14.html (332 words)

	Common breakpoint in virtual time logic simulation for parallel processors - Patent 5442772
		A logic simulator as set forth in claim 15 wherein each of said logic simulation program means receives an input from or supplies an output to another of said processors or computing nodes, and predicts an input when unavailable from another of said processors or computing nodes.
		Logic simulator 10 comprises a host computer 12 with a known communication facility (not shown), a multiplicity of processing nodes 14a-h each with a respective known communication facility (not shown), and a known cross bar switch 16 which interconnects the host computer to the parallel processors and the parallel processors to each other.
		Logic simulation advances and is processed according to steps 110, 111, 113, 115 and 112 unless and until the logic simulation is rolled back to a time before the break point.
	www.freepatentsonline.com /5442772.html (7395 words)

	EDN Access--02.03.97 Digital-Simulation Logic-Value Systems (Site not responding. Last check: 2007-10-24)
		Finally, the simulator considers the resistive FET, which clearly presents a WH (weak-high) value to the node, but the simulator doesn't remember that the DX value is the result of the ambiguity between a Z and a DH, so its only course of action is to leave the node set to a DX value.
		Then, when the simulator subsequently evaluates the normal FET, its algorithms may be sufficiently powerful to recognize the fact that combining a definite WH with either a Z or a DH means that the final value assigned to the node should be some flavor of a logic 1.
		When the interval-value simulator compares the CL from the capacitive element with the ambiguity between the Z and DH values arising from the normal FET, the resulting intermediate value is the interval encompassing the range between CL and DH.
	edn.com /archives/1997/020397/03DF_06.htm (2608 words)

	Simulation Speed in Hardware Description Language
		The numbe r of simulation test cases required to verify a design is more or less directly proportional to the size of the state space and the number of interconnections i n the combinational logic.
		In a simulator at a higher level of abstraction, the operation wo uld be the logical operator applied to all the bits of the bus at once.
		That is, a simulation model must tran sition from one state to another in the same way as the real system being modele d (the abstract states and state transitions must be a homomorphic image of the real system's state space).
	www.angelfire.com /in/rajesh52/simspeed.html (1928 words)

	Computer Aids for VLSI Design
		In functional-level simulators, connectivity may be explicitly shown by wires carrying signals between functional units, or implicitly shown by functional units calling (in the manner of subroutines) other functional units with parameters.
		Simulation results can be useful in verifying the correctness of a design before implementation, as well as for diagnosing implementations of a design.
		The second method views the simulation as a series of events, where an event is a change to a node.
	www.rulabinsky.com /cavd/text/chap06-5.html (2611 words)

	Programmable look up system - Patent 4736338
		The simulation of such designs is used to test the operation of the design before the design is physically implemented as a printed circuit board or an integrated circuit.
		Software logic simulators provide a performance of a few thousand events per second; firmware simulators, a performance of a few tens of thousand events per second; and hardware simulators, a performance of a few hundred of thousand events per second.
		An objective of this invention is to facilitate the use of memoried logic elements with hardware logic simulators.
	www.freepatentsonline.com /4736338.html (2513 words)

	Formal Validation
		The simulator's waveform output, which is a prediction of the response of the circuit to the applied inputs, is then compared to the response of the previous design stage's description to the same inputs to verify that the responses are consistent.
		After validation, the logic design step is performed, in which the RTL model of the circuit is used as an input to a logic synthesis tool to create a gate level implementation of the circuit.
		The simulator's waveform output, which is a prediction of the response of the circuit to the applied inputs, is then compared to the response of the reference model of the circuit (typically created during the previous design stage) to the same inputs to verify that the responses are consistent.
	www.veritable.com /Computer/Formal_Validation/formal_validation.html (2683 words)

	Valeria Bertacco: Stanford Research Communication Program
		A logic simulator uses a description of the microchip behavior, which is usually already available as part of the design process, takes some inputs provided by the engineers, and computes the output that the microchip would generate with those specific inputs.
		If the simulated and expected results match, the circuit is operating correctly at least in that specific case; otherwise there is a possible bug in the circuit.
		For instance, if the microchip was for a hand calculator, one possible logic simulation would be to provide the input 3 times 5 to the logic simulator and check that the output is actually 15.
	www.stanford.edu /group/i-rite/statements/2003/bertacco.htm (677 words)

	VHSIC Hardware Description Language - LearnThis.Info Enclyclopedia (Site not responding. Last check: 2007-10-24)
		A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered.
		VHDL is in fact a fairly general-purpose programming language, provided that you have a simulator on which to run the code.
		However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable.
	encyclopedia.learnthis.info /v/vh/vhsic_hardware_description_language.html (611 words)

	Logic Simulation \| Tutorial-Reports.Com (Site not responding. Last check: 2007-10-24)
		Logic simulation and verification are used to verify the functionality described by a design description against output values expected at the output ports of a digital integrated circuit.
		As a logic element is evaluated its output is decided on the basis of its inputs and time stamp of output is decided by time stamp of last arriving token and delay of the logic element.
		If an input of a logic element is driven by one of its output or output of a forward logic element then it leads to deadlock.
	www.tutorial-reports.com /hardware/asic/simulation.php (922 words)

	The Challenges of an Embedded Software Engineer
		Simulators have been around almost as long as processors themselves, but their use and complexity has changed to make them more usable for today’s high-level embedded software developers.
		The ISS simulates the instruction set of the processor architecture and varies in the degree of timing and peripheral accuracy from “cycle-accurate” to “instruction accurate” with different levels of cache and memory access timing accuracy.
		Since the processor architecture is not being designed by the hardware engineer, it doesn’t require simulation in the logic simulator, allowing the peripheral devices and the “real” hardware to be simulated in the logic simulator.
	www.embeddedtechjournal.com /articles_2005/20051004_mentor.htm (1544 words)

	DigitalToolboxManual
		However, since the simulation process uses a simplified model of the digital network, to ensure that simulation may be carried out in a reasonable time, it is vitally important that the designer understands the model's limitations.
		During a simulation pass the values of any input nodes are altered directly in the table, then all the code produced for the circuit is executed sequentially and at the end the table will contain the resultant values of every node.
		Several of the areas in which the newer interpreted simulator wins over the compiled version are the handling of feedback in sequential circuits, the ability to use assignable delay models and the ability to perform race and hazard analysis.
	www.btinternet.com /~rjevans/dtbx/DigitalToolboxManual.html (6701 words)

	VHSIC hardware description language - Wikipedia, the free encyclopedia
		The idea of being able to simulate these "documents" was so obviously attractive that logic simulators were developed that could read the VHDL files.
		VHDL has a syntax that is identical to the Ada with an added superset of constructs to handle the parallelism inherent in hardware designs.
		VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog.
	en.wikipedia.org /wiki/VHDL-93 (686 words)

	ACCELERATING SWITCH-LEVEL SIMULATION BY FUNCTION CACHING
		Logic simulators, which operate at relatively high speeds, lack in their abilities to model important aspects of MOS design such as charge sharing, ratio logic, and bidirectionality of devices.
		Switch-level simulators such as MOSSIM II [4] and RSIM [9] partition digital circuits into subnetworks of source/drain connected transistors and apply an evaluation procedure to the subnetwork which estimates the new state of the electrical nodes within the subnetwork given their initial state and the conductance of the transistors.
		The methods presented can, in principle, be applied to other switch-level simulators such as [6] [9] [1], although it may be necessary to represent information other than state, such as voltage-levels and delay, into the keywords and actionwords.
	www.sigda.org /Archives/ProceedingArchives/Dac/Dac91/papers/1991/dac91/14_2/14_2.htm (2582 words)

	LAB SIMULATION SOFTWARE, electronics, electro-mechanical, PLC allen bradley ladder logic, simulators
		These simulators are bundled with our CD-ROMs to provide a seamless transition from the theory to the lab.
		In addition, these simulators can also be purchased separately and used as stand-alone learning tools in classrooms, laboratories, desktops, and test benches.
		By using this simulator, students gain a practical understanding of DC fundamentals including current, voltage, resistance, Ohm's law, power, series circuits, parallel circuits, and series-parallel circuits.
	www.logicdesign.com /inside/sim.html (292 words)

	International Journal of Electrical Engineering Education: Teaching programmable logic controllers using ...
		Programmable logic controllers (PLCs) have progressed rapidly since their inception in the early 1970s, and are now widely used in the manufacturing, process and utility industries.
		The programmable logic control simulators described in the literature6-8 are, in general, designed to represent only a subset of the capabilities of most industrial PLCs.
		The simulated liquid crystal display (LCD) screen comprises three areas: a message line which displays different information depending upon the mode of the programmer; a mode line which indicates the current mode of the programmer; and a ladder diagram area which can consist of up to eight rungs.
	www.findarticles.com /p/articles/mi_qa3792/is_200010/ai_n8907349 (1369 words)

	Dr. Dobb's \| Hierarchical Logic Simulation \| July 22, 2001
		Unlike traditional event simulators, the simulation strategy I describe here does not use the concept of a global event queue or global clock to synchronize the events that are propagated through components within the simulation.
		During hierarchical simulation, a component must have a mechanism through which it can communicate with components in the same level of the hierarchy and with components in lower levels (that is, its subcomponents).
		The simulation of a circuit, represented using the strategy just described, is similar to a depth-first traversal of the 3D hierarchy of components along the wires and ports.
	www.ddj.com /184410878 (3644 words)

	EETimes.com - How performance analysis aids system design
		Also, with the execution speed of the logic simulator limited to 10 or 20 instructions per second, not enough software can be run to provide meaningful results.
		Logic simulators can be instrumented to provide bus and memory transactions, but without the correlation back to software execution, it delivers hardware performance data at best, not the system analysis presented here.
		Integrating a hardware simulator with the ISS significantly improves the accuracy of software profiling, displaying the precise elapsed time in nanoseconds for each software function, including the time to service interrupts asserted by the hardware during function execution.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=16500914 (1925 words)

	simtools (Site not responding. Last check: 2007-10-24)
		Simulation tools, simulation models, and simulation methods vital to successful high-speed design are covered in detail.
		Several commonly used simulators are demonstrated by simulating actual circuits such as GTL buses, LVDS buses, ECL circuits and RamBus circuits.
		SI simulators are used in class to demonstrate the effects of features such as stubs, vias, loads, and connectors on transmission line behavior.
	www.speedingedge.com /html/simtools.html (564 words)

	Computer Aids for VLSI Design
		Logic-level simulators may simulate at the device level or at the gate level.
		Gate-level simulators use the same logic values as switch-level simulators use, but circuit elements are modeled at the gate rather than the transistor level.
		Input to gate-level simulators is a schematic of the circuit in terms of logic gates (for example, NAND, OR, D-flip flop) and wires.
	www.rulabinsky.com /cavd/text/chap06-3.html (512 words)

	Automatic Generation of Compiled Simulations through Program Specialization
		Compiled simulation executes much more rapidly than interpreted simulation because the overhead of tranversing and interpreting the data structure that describes the circuit is done only once, when the compiled simulator is created.
		Some simulation algorithms, such as the demand-driven algorithm in BACKSIM [3], had not, prior to this work, been used as the basis for compiled simulation.
		In this experiment, the simulator (and therefore the compiled simulator) returned the value of each node during settling, that is, the complete history of the simulation itself.
	www.sigda.org /Archives/ProceedingArchives/Dac/Dac91/papers/1991/dac91/14_1/14_1.htm (4558 words)

	Co-Verification Methodology for Platform FPGAs
		The bottlenecks in simulation are due to the accurate, but slow, logic simulators.
		Given that processor-to-logic interaction is mostly through read-write cycles to memory – fetching instructions, accessing peripheral registers, and such – the overall simulation speed is dramatically increased by diverting most routine CPU-to-memory transactions to run through the faster CMS instead of through the logic simulator.
		Typically, this means the simulator bottleneck is only a factor in less than one percent of the software-hardware transactions, thus providing a significant overall throughput advantage versus pure RTL simulation.
	www.fpgajournal.com /articles_2005/20050222_mentor.htm (1868 words)

	[No title]
		Logic simulators provided a much easier way to observe and correct design errors.
		Even though logic simulation turned out to be much easier than debugging prototypes, hardware engineers still struggled to incorporate the software into these logic simulations.
		Instruction set simulators (ISS) and real time operating system (RTOS) simulators were developed to allow software to be debugged on a workstation using source level debuggers.
	archive.chipcenter.com /asic/tn009.html (326 words)

	Untitled Document
		We will use two different types of circuit simulators that differ in the way the circuit is constructed.
		simulators require that you build the circuit using standard logic symbols.
		simulators require that you describe the circuit in specific higher level languages that resemble programming languages in many respects.
	members.tripod.com /~Comp_Design/Download/Simulators.html (388 words)

	Whitepapers
		The concept of logic simulation has since been extended to allow for other representations of the hardware that are not the final implementation, including logic emulation systems or other prototyping methods.
		Because they are unfamiliar with logic simulation and emulation tools, they pass the image file over to the verification engineers who run the test.
		As simulations are run, RCC stores checkpoints on the disk of the workstation that contain values for all of the memory elements of the design.
	www.verisity.com /resources/whitepaper/debugging.html (1724 words)

	Extensible Hierarchical Object-Oriented Logic Simulation with an Adaptable Graphical User Interface (Site not responding. Last check: 2007-10-24)
		Simulators must also be easily extensible so that the behaviour and performance of a wide variety of systems may be studied.
		Central to the simulation technique is the concept of local time, in which each entity being simulated maintains its own notion of time throughout the simulation.
		As a result, the simulator engine could be configured to employ a different graphical interface and the graphical interface can be adapted for a variety of existing text-based simulator engines.
	web.cs.mun.ca /~donald/msc/thesis.html (542 words)

	EETimes.com - A primer on processor-based emulation
		During each time step, each processor is capable of performing any 4-input logic function using as inputs the results of any prior calculation of any of the processors and any design inputs or memory contents.
		The compiler also has to take into account simulation acceleration connections, tri-state bus modeling, memory modeling, non-uniform processor connectivity, logic analyzer probing and triggering, and other factors.
		Since processor-based emulators schedule logic operations to occur in sequence, it is easy to add a constraint on the timing within the emulation cycle on individual (or groups of) output signals to control the timing to a very high resolution relative to other output signals.
	www.eetimes.com /news/design/features/showArticle.jhtml?articleID=51000078 (3000 words)

	Lab 1: Logic Gates
		Since it can be expensive to build an actual computer circuit with physical components, computer scientists use software-based Boolean logic simulators to construct and test computer circuit diagrams before the physical version.
		In this lab you are going to use a Java applet Boolean logic simulator to construct and test computer circuits that illustrate each basic Boolean gate, simple computer circuits and memory flip-flops.
		A circuit built using the simulator is invalid if there are excess gates or not all the gates are properly connected.
	wps.aw.com /aw_brookshear_compsci_8/0,8808,1214158-content,00.html (959 words)

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