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Topic: MOSI protocol


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In the News (Sun 20 Apr 14)

  
 MoSI Program
MoSI is a cooperative effort among organizations, researchers, and bird banders in Mexico, Central America, and the Caribbean aimed at evaluating the quality of winter habitats for migratory landbirds.
The monitoring goal of MoSI is to provide estimates of monthly, overwintering, and annual survival rates and indices of late winter physical condition for a suite of 25 landbird species for a variety of habitats and geographic regions.
The basic MoSI field protocol calls for five monthly (November through March) pulses of mist net operation on a 20-ha study area (the MoSI station) established in a habitat of interest where at least one MoSI target species can be captured in substantial numbers.
www.birdpop.org /MoSI/MoSI.htm   (713 words)

  
 [No title]
The OIW mOSI work is supported by EWOS which is cooperating with the OIW on progression of the current draft of mOSI.
The object identifiers received when a protocol is registered are used to identify the application's abstract and transfer syntaxes to the OSI Presentation service.
The t_open() and t_bind() are called by the CO_CLIENT protocol machine with the parameters specified for these functions in the XTI manual as modified by appendix H for mOSI -- in particular, the addr structure of t_bind() shall contain a local OSI presentation address.
www.opengroup.org /tech/rfc/mirror-rfc/rfc43.0.txt   (3844 words)

  
 Cache coherent computer system that minimizes invalidation and copyback operations - US Patent 5706463   (Site not responding. Last check: 2007-10-11)
The method of claim 14, wherein the the first coherency protocol is a MOESI coherency protocol and the second coherency protocol is a MOSI coherency protocol.
For example, one type of cache coherency protocol which is referred to as the MOESI protocol maintains a set of five states for datablocks stored in the cache memories.
Such an embodiment enables the memory interconnect subsystem 18 to function as a reflective memory wherein a copyback operation on a load miss to a "modified" datablock causes the datablock to be written back into the main memory 14 and causes the requesting processor to transition to the "shared" state.
www.patentstorm.us /patents/5706463.html   (3688 words)

  
 Interfacing SPI Peripherals to the MAX7651 Processor - Maxim/Dallas
It defines the basics of the SPI protocol, the signals and the four transfer variations for the SCK signal.
MOSI (Master Output/Slave Input): Data is transmitted out of this pin if the chip is a Master and into this pin if the chip is a Slave.
The SPI protocol defines four combinations of SCK phase and polarity with respect to the data.
www.maxim-ic.com /appnotes.cfm?appnote_number=802   (902 words)

  
 SPI, MCP3208, MPX4115
This application note discusses an implementation of the Motorola SPI protocol and illustrates an SPI interface with a Microchip MCP3208 eight channel 12-bit A/D. It also illustrates how the 12-bit A/D may be used with a Motorola MPX4115AP or MPX4115AS to measure atmospheric pressure and convert this to barometric pressure..
Data is then clocked to the slave, beginning with the most significant bit on the MOSI output and at the same time, receiving data bits on the MISO signal lead.
Note that the most significant bit of X is tested and the MOSI output is set to the appropriate state.
www.phanderson.com /picaxe/spi.html   (1373 words)

  
 PracticalEmbeddedJava
MOSI - Master Out Slave In MOSI is the SPI data bit being sent from the master controller to the SPI slave device.
MOSI is the master data output and is connected to the slave data input.
One MOSI signal can be shared by multiple slaves if they each have their own chip select.
www.practicalembeddedjava.com /SPI/spi.html   (1548 words)

  
 Coherence protocol   (Site not responding. Last check: 2007-10-11)
In computer science, a coherence protocol is a protocol in systems with distributed memory (distributed shared memory systems, including multiprocessors), which maintains memory coherence according to specified consistency model.
Examples of such protocols are the MESI protocol, MSI protocol, MOSI protocol (more generally: the MOESI protocol) and many others.
Most of the cache protocols in multiprocessors are supporting sequential consistency model, while in software distributed shared memory more popular are models supporting release consistency or weak consistency.
www.portaljuice.com /coherence_protocol.html   (90 words)

  
 Program --- Vol 30, No 1, January 1996 - ARTICLES
Protocol Data Units (PDUs) are the means of communication between the origin and the target.
For these reasons, it has been suggested that the two protocols converge, and at the time of writing, a decision is about to be taken as to whether SR adopts Z39.50-1995 in its next version.
Several limitations of the SR protocol (such as the lack of index scanning and proximity searching) became apparent during the course of the project.
www.aslib.co.uk /program/1996/jan/02.html   (8189 words)

  
 Cache coherency - Wikipedia, the free encyclopedia
Distributed shared memory systems mimic these mechanisms in an attempt to maintain consistency between blocks of memory in loosely coupled systems.
Various models and protocols have been devised for maintaining cache coherency, such as the MESI protocol, MSI protocol, MOSI protocol and the MOESI protocol.
Choice of consistency model is crucial to designing a cache coherent system.
en.wikipedia.org /wiki/Cache_coherency   (301 words)

  
 [No title]
Introduction The upper-layer protocols of the OSI model are large and complex, mostly because the protocols they describe are rich in function and options.
This document presents the protocol elements required by the OSI upper layers when supporting a connection-oriented application with only basic communication requirements - that is to create a connection, optionally negotiate the data representation, send/receive data, close a connection and abort a connection.
In this document, the protocol elements needed are given in terms of the octet sequences that comprise the 'envelope' around the application data.
www.isi.edu /in-notes/rfc1698.txt   (4667 words)

  
 World Intellectual Property Organization   (Site not responding. Last check: 2007-10-11)
If the cache protocol does not require a processor to provide data in response to a request, system memory 100 may be configured to provide the data.
A cache protocol can define what access rights a processor has to a cache line and whether the processor is to provide the cache line in response to a request.
In the MOSI protocol, access rights can be granted or revoked based on the current state of the access rights of a cache line and the type of request.
www.wipo.int /ipdl/IPDL-CIMAGES/view/pct/getbykey5?KEY=01/09728.010208&ELEMENT_SET=DECL   (5456 words)

  
 TBITS-6.2 The Industry/Government Open ... Continued
IR addresses retrieval (but not update) of information and the IR protocol specifies basic information retrieval operations, a common syntax for queries and the means to express their semantics, and the means to allow the partner systems to share an understanding of the information retrieved.
The routing protocols supported and the required capabilities of those protocols are a function of the role that an IS must be capable of operating in.
The encapsulation scheme for the transmission of OSI network layer protocols on frame relay subnetworks is consistent with the procedures for protocol identification specified in Part 3, clause 9 of the Workshop Agreements.
www.control.auc.dk /~henrik/undervisning/netpro/litt/62S2-3_e.html   (11329 words)

  
 Microcontroller Interfaces, Part 2
In this part, I'll cover the specifics of their protocol formats.
CPHA determines on which clock edges data is shifted in and out (CPHA=0 MOSI data is shifted out on falling edge, MISO data is shifted in on rising edge).
Figure 4 shows the original Microwire protocol (which is older than SPI) that has fixed clock polarity and clock phase: SI is latched (data shifted in) on the rising edge of the SK clock and SO changes (data shifted out) on the falling edge.
www.ucpros.com /work%20samples/Microcontroller%20Communication%20Interfaces%202.htm   (1186 words)

  
 Serial bus page
The maximum number of devices connected to the I2C bus is dictated by the maximum allowable capacitance on the lines, 400 pF, and the protocol's addressing limit of 16k; typical device capacitance is 10 pF.
Serial protocols such as SPI, a chip-select input is required to enable the IC.
This protocol is also used for example by Microchip and Fairchild in their serial EEPROMs.
www.epanorama.net /links/serialbus.html   (2621 words)

  
 RFC NNN
For the purposes of this RFC, the mOSI model is as shown in Figure 1.
To aid migration, mOSI provides defaults for both application and presentation context such that byte stream oriented applications don't need to be concerned with contexts.
While the mOSI ISP will not mandate how it should be implemented, for efficiency, as was done in Xosi [EWOS], an annex of the ISP encourages lumping the upper 3 layers of OSI together into one module and using predefined PCI (protocol control information) wherever possible, particularly for the protocol used for exchanging application data.
www.opengroup.org /tech/rfc/rfc43.0.html   (3651 words)

  
 System with arbitration scheme supporting virtual address networks and having split ownership and access right ...   (Site not responding. Last check: 2007-10-11)
In a standard broadcast protocol, requests arrive at all devices in the same order, and the access rights of the processors are modified in the order in which requests are received.
In certain situations or configurations, systems employing broadcast protocols may attain higher performance than comparable systems employing directory based protocols since coherence requests may be provided directly to all processors unconditionally without the indirection associated with directory protocols and without the overhead of sequencing invalidation and/or acknowledgment messages.
As used herein, a directory based cache coherence protocol is any coherence protocol that maintains a directory containing information regarding cached copies of data, and in which coherence commands for servicing a particular coherence request are dependent upon the information contained in the directory.
www.freepatentsonline.com:9003 /6877056.html   (18989 words)

  
 MOSI protocol -- Facts, Info, and Encyclopedia article   (Site not responding. Last check: 2007-10-11)
MOSI protocol -- Facts, Info, and Encyclopedia article
This is an extention of the basic (additional info and facts about MSI) MSI (additional info and facts about cache coherency) cache coherency protocol.
It adds the Owned state, which indicates that the current processor owns this block, and will service requests from other processors for the block.
www.absoluteastronomy.com /encyclopedia/m/mo/mosi_protocol3.htm   (56 words)

  
 SPI Protocol
The communications protocol is half-duplex, with the Easy GUI client acting as master.
Since this is an ASCII protocol, it takes two bytes to send one-byte variables and RPCs.
For example, the variable 0x1A would be transmitted as 0x31, 0x41, where 0x31 is the ASCII representation of the high nibble"1" and 0x41 is the ASCII representation of the low nibble "A".
www.amulettechnologies.com /support/help/SPIprotocol.htm   (1087 words)

  
 United States Patent Application: 0040006453
The method of claim 4, wherein the cache architectural component comprises cache coherency protocol.
The total cache size, cache line size, cache associativity, cache sharing, cache write type, and cache coherency protocol along with their values or respective ranges are provided.
Preliminary experiments and simulations are performed uniformly over the sample space of the cache architecture of interest, e.g., Cache Architecture 1, and a set of preliminary cache data is generated.
appft1.uspto.gov /netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20040006453".PGNR.&OS=DN/20040006453&RS=DN/20040006453   (4253 words)

  
 Society Fresh : Article 'Cache coherency'   (Site not responding. Last check: 2007-10-11)
Directory-based coherence protocols are a set of cache coherence protocols, that is, protocols which ensure cache coherence or memory coherence between multiple nodes of multiprocessor or distributed shared memory systems, such as ccNUMA.
In some protocols, these nodes then respond with data (these are called 3-hop-miss or cache-to-cache transfer protocols).
In home-based protocols, each page has its own home node, and its corresponding directory is located on that node, containing only traces of pages from this node.
www.society-fresh.net /DisplayArticle173748.html   (995 words)

  
 Models for Open System Protocol Development : A Technical Report (1994) - UDT Series on Data Communication Technologies ...
Instead, another network protocol suite, the Transmission Control Protocol/Internet Protocol (TCP/IP) which originated with the ARPANET of the Advanced Research Project Agency in the United States Department of Defense is used in many networks.
The Internet protocols are organized in a layered model like OSI protocols, but the model is simpler than the OSI and the tasks are not divided exactly as they are in the OSI model.
In the mOSI, the session, presentation and ACSE part of the application are independent of the transport protocol.
www.ifla.org /VI/5/reports/rep6/613.htm   (2612 words)

  
 The Daraja by Mosi Pacha
A new technology called Voice Over Internet Protocol, or VoIP, enables voice signals to be sent over the Internet instead of through traditional telephone lines.
In its simplest description, you just plug your current landline phone into a small box, which is provided when you subscribe to the service.
For those of us who use the Internet on a regular basis, e-mail can be the most efficient means of communicating with the outside world.
www.expoupdate.com /daraja.htm   (7923 words)

  
 MOESI protocol - TheBestLinks.com - Cache coherency, MESI protocol, MSI protocol, MOSI protocol, ...
MOESI protocol - TheBestLinks.com - Cache coherency, MESI protocol, MSI protocol, MOSI protocol,...
MOESI protocol, Cache coherency, MESI protocol, MSI protocol, MOSI protocol
This is a full cache coherency protocol that encompasses all of the possible states commonly used in other protocols.
www.thebestlinks.com /MOESI_protocol.html   (164 words)

  
 29/7/2003 -- Zambia Formulates Black Rhino Recovery Plan
At the apex of regional wildlife management, there is the SADC Protocol on Wildlife Conservation and Law Enforcement, signed by heads of member states in August 1999.
The protocol recognizes that the viability of wildlife resources in the region requires collective cooperative action by all the 14 member countries.
Winnie Musonda, a representative of the United Nations Development Programme (UNDP), wonders at the general decline of the Zambian economy due to the falling prices of copper, and she suggested that the country's wildlife resource be an alternative source of income.
www.forests.org /articles/reader.asp?linkid=24573   (1188 words)

  
 Cache coherency - TheBestLinks.com - CPU, Memory, Multiprocessor, MESI protocol, ...   (Site not responding. Last check: 2007-10-11)
Cache coherency, CPU, Cache, Memory, Multiprocessor, MESI protocol, Consistency...
Cache coherency (alternatively cache coherence or cache consistency) is the property that accessing a cache gives the same value as the underlying data, even when the data was modified by a different process after the caching was performed.
Most of the cache protocols in multiprocessors are designed to support sequential consistency.
www.thebestlinks.com /Cache_coherency.html   (188 words)

  
 Introduction to Serial Peripheral Interface   (Site not responding. Last check: 2007-10-11)
In fact, without a communication protocol, the SPI master has no knowledge of whether a slave even exists.
In some applications, a higher-level protocol is not needed and only raw data are exchanged.
In other applications, a higher-level protocol, such as a command-response protocol, may be necessary.
www.embedded.com /shared/printableArticle.jhtml?articleID=9900483   (987 words)

  
 Interfacing the DS1620 to the Motorola SPI Bus - Maxim/Dallas
Lastly, the RST-bar is unlike a CS-bar (chip select) signal in that RST-bar must be high from the beginning of a transfer (protocol) to the end of all transfer of data (e.g.
The resistor is necessary to prevent contention between the output of the tri-state buffer on the MOSI line and the DQ pin of the DS1620, because after a READ command protocol has been received by the DS1620, its DQ pin changes direction from input to output in a few hundred nanoseconds.
With the protocol sent, the DIR is changed from low to high (indicating now a READ transfer) because the DS1620 is ready to send out the 9-bit value.
www.maxim-ic.com /appnotes.cfm/appnote_number/85   (938 words)

  
 Dan Henry's 8052.com Contributions
BCC 15.1 is a point-to-point protocol and is virtually identical to "PPP in HDLC-like Framing" defined by Internet RFC 1662 using the minimal transparency implementation.
The document will be updated as part of a larger work having the goal of demonstrating the use of well-defined protocols in lightweight systems.
Tiny RPC is a trivial protocol compared to full-blown RPC protocols found on larger networked systems.
www.8052.com /users/dhenry   (845 words)

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