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Topic: Memory (disambiguation)

	Memory Alpha:Disambiguation - Memory Alpha, the Star Trek Wiki
		Disambiguation in Memory Alpha is the process of resolving the conflict that occurs when articles about two or more different topics have the same natural title.
		Memory Alpha thrives on the fact that making links is simple and automatic: as you're typing in an edit window, put brackets around Enterprise (like this: [[Enterprise]]) and you'll have a link.
		While it's generally okay for disambiguation pages to be orphans – it's more appropriate for other articles to link to the specific subjects rather than to the disambiguation page – we want to avoid cluttering the list of orphaned pages with these intentional orphans.
	www.memory-alpha.org /en/wiki/Memory_Alpha:Disambiguation (627 words)

	Memory - Wikipedia, the free encyclopedia
		Although traditional studies of memory began in the realms of philosophy, the late nineteenth and early twentieth century put memory within the paradigms of cognitive psychology.
		A basic and generally accepted classification of memory is based on the duration of memory retention, and identifies three distinct types of memory: sensory memory, short-term memory, and long-term memory.
		A further major way to distinguish different memory functions is whether the content to be remembered is in the past, retrospective memory, or whether the content is to be remembered in the future, prospective memory.
	en.wikipedia.org /wiki/Memory (1569 words)

	Memory (computers) - Wikipedia, the free encyclopedia
		An analogy is to think of the storage as human memory, with the hard disk as long-term memory, and the memory as short-term memory.
		Read-only memory, or read-write is a distinction based on properties of the memory.
		The term memory identifies data storage that comes in the form of chips, and the word storage is used for memory that exists on tapes or disks.
	en.wikipedia.org /wiki/Computer_memory (1117 words)

	[No title] (Site not responding. Last check: 2007-11-04)
		Memory disambiguation buffers are used to perform bypass in situations where data dependencies occur in system that allows speculative and out-of-order which are used to resolve potential problems in deciphering the address tags, also store tag information.
		A memory dependency is false if evaluation of the memory location for a load operation appears to be the same as that for the memory location of a prior store operation, but in actuality is not the same because the aliases point to different physical memory locations.
		In one embodiment, the memory structure is a memory disambiguation buffer.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=03/102784.031211&ELEMENT_SET=DECL (3828 words)

	Identifying pure pointers to disambiguate memory references - Patent 7127710
		Disambiguation may be effected by identifying pure pointer variables within the computer program and applying at least one disambiguation rule to memory references associated with the pure pointers to determine whether the references are disjoint.
		Alternately, disambiguation of memory references in accordance with another embodiment may be implemented by other programs that analyze the control and data flow of programs, such as software understanding or testing tools.
		Pure pointer identification and its use to disambiguate memory references may be used for any suitable programming tool or analyzer, such as a compiler or interpreter.
	www.freepatentsonline.com /7127710.html (2726 words)

	Memory disambiguation for large instruction windows - US Patent 6591342 (Site not responding. Last check: 2007-11-04)
		The memory disambiguation apparatus of claim 15 wherein the at least one overflow indicator comprises an array of counters, each counter of the array of counters having a value that reflects a number of overflow occurrences.
		The memory disambiguation apparatus of claim 22 further comprising a second queue having a second plurality of queue entries, wherein each of the plurality of second queue entries corresponds to one of a plurality of load instructions in the instruction window.
		In another embodiment, a memory disambiguation apparatus includes a queue configured to hold all of the store instructions that are in an instruction window, and a set-associative buffer configured to hold a subset of the store instructions that are in the instruction window.
	www.patentstorm.us /patents/6591342.html (9783 words)

	Peer to Patent, Community Patent Review
		Hence, in some cases, a memory operation may be unnecessary as the original data that was stored to memory and immediately re-loaded from memory is still present in one of the registers of the processor.
		The disambiguation may compare the actual load and predicted store addresses, which may be utilized to either validate the prediction or indicate a misprediction by triggering a pipeline reset (also referred to as a “nuke”) to clear the pipeline and/or refetch the respective load instruction (and instructions following the load instruction).
		Moreover, disambiguation may be utilized for forwarding, e.g., where a store instruction is either predicted to forward to a load or is not predicted to forward to a load.
	www.peertopatent.org /patent/26/overview (5463 words)

	Research (Site not responding. Last check: 2007-11-04)
		Memory disambiguation is critical in OoO processors because it affects the correctness of the processor.
		In a shared-memory multi-processor system, memory disambiguation also includes maintaining the program order of load-load pair in one thread and the ordering of load-store pair across multiple threads.
		We revisited the idea of speculative memory disambiguation, which dose not perform exact disambiguation at the execution stage of a load, and thus is more flexible.
	www.ece.rochester.edu /~hrk1/Research.htm (1390 words)

	[No title] (Site not responding. Last check: 2007-11-04)
		In this paper, we examine the notion of memory distance as it is applied to the instruction space of a program and to feedback-directed optimization.
		Memory distance is defined as a dynamic quantifiable distance in terms of memory references between two accesses to the same memory location.
		Additionally, we apply memory-distance analysis to memory disambiguation in out-of-order issue processors, using those distances to determine when a load may be speculated ahead of a preceding store.
	www.cs.mtu.edu /html/abstracts/fang-abstract.txt (241 words)

	Glossary
		Ambiguous memory accesses are a pair of memory accesses that may refer to the same address in memory.
		A contiguous array of memory locations, commonly referred to as “the stack”, used in many processors, to save the state of the calling procedure, pass parameters to the called procedure and store local variables for the currently executing procedure.
		Data with spatial locality is data with memory addresses close to the data or instructions currently in use.
	www.ncsa.uiuc.edu /UserInfo/Resources/Hardware/XeonCluster/Doc/Intel_8.0.044/training/templ/gcompopt.htm (3012 words)

	An Overview of the Intel IA-64 Compile
		Similarly, moving memory references across function calls requires knowledge of what is modified or referenced by the function call.
		The compiler may disambiguate these two memory references either by determining that a and b are different memory objects or that field1 and field2 are non-overlapping fields.
		In general, in order to disambiguate this pair of memory references, the compiler must perform points-to analysis [12], which determines the set of memory objects that each pointer could possibly point to.
	www.intel.com /technology/itj/q41999/articles/art_1e.htm (905 words)

	[No title] (Site not responding. Last check: 2007-11-04)
		Memory disambiguation is performed at run-time with the support of two new instructions supplied by the ISA (preload and check) and recovery blocks inserted by the compiler.
		If there is an actual memory dependence that can’t be determined at compile time, then there could be a significant performance decrease if the load is moved above the dependent store by the compiler (the recover block would have to be executed every time).
		In general the true memory dependence conflicts were a small percentage of the total conflicts (true memory dependence, load-load, and load-store).
	www.cs.princeton.edu /courses/archive/fall99/cs597d/restricted/obs/obs13/gw.html (343 words)

	Memory Alpha talk:Disambiguation - Memory Alpha, the Star Trek Wiki
		Alpha, though, could be a disambiguation page for Alpha (Jem'Hadar), Alpha Quadrant and Alpha system and others, but definitely shouldn't include links to articles like Treaty of Alpha Cygnus IX (no one would refer to that treaty as simply "Alpha").
		Now, a disambiguation page is often used to list articles that share a part of their name - most of those article would never be addressed by just that part, though, so the usefulness of the disambiguation is dubious at best.
		As already mentioned above, I created the template {{disambiguation link}} (to link to a disambiguation page located at Title (disambiguation)), and also {{ep disambiguation}} (to link to an episode article located at Title (episode)) as well as {{disambiguate}} (using a parameter, to link to another page if there are only two meanings of a term).
	memory-alpha.org /en/wiki/Memory_Alpha_talk:Disambiguation (2739 words)

	Memory Disambiguation for General-Purpose Applications (Site not responding. Last check: 2007-11-04)
		Memory disambiguation is a technique for removing spurious data dependences that severely limit the compiler's freedom of code-scheduling.
		This paper is a survey of several recently proposed memory disambiguation schemes that can handle pointer dereferences.
		Static disambiguation uses data-flow analysis to compute an approximation of the set of memory aliases at each program point.
	www.cs.ubc.ca /local/reading/proceedings/cascon95/htm/francais/abs/luk.htm (172 words)

	A Memory-Based Model of Syntactic Analysis
		Most probabilistic disambiguation models therefore build directly on that work: they characterize the probabilities of sentence-analyses by means of a "stochastic grammar", constructed out of a competence grammar by augmenting the rules with application probabilities derived from a corpus.
		Linguistic disambiguation involves classification under an ambiguous definition of the "case description language", i.e., the formal representation of the utterance analyses, which is usually a grammar.
		In DOP, this measure is simplified during parsing to string-equivalence and complicated during disambiguation by a probabilistic ranking of the alternative trees of the input sentence.
	iaaa.nl /rs/jetai/jetai.html (13442 words)

	Memory Alpha:Policies and guidelines - Memory Alpha, the Star Trek Wiki
		Memory Alpha:Policies and guidelines - Memory Alpha, the Star Trek Wiki
		Memory Alpha has some policies that have been proposed by the administrators and generally accepted by the members.
		Add that page to your watchlist to be kept up-to-date.
	memory-alpha.org /en/wiki/Memory_Alpha:Policies_and_guidelines (407 words)

	[No title] (Site not responding. Last check: 2007-11-04)
		Improving Instruction-Level Parallelism by Loop Unrolling and Dynamic Memory Disambiguation
		This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism.
		The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming and static memory disambiguation, the ILP of memory-intensive benchmarks can be increaed by as much as 300 percent over loops where only loop unrolling, register renaming and static memory disambiguation has been performed.
	american.cs.ucdavis.edu /Micro28/html/abst13.html (179 words)

	[No title] (Site not responding. Last check: 2007-11-04)
		Memory disambiguation, or alias analysis, is a key component of modern optimizing compilers.
		Any optimization that reorders or changes code containing memory operations must analyze the memory references to ensure that the original semantics of the program are not changed.
		In this paper, we present a new algorithm for dynamic memory disambiguation for array references that allows us to overcome limitations of static analysis.
	american.cs.ucdavis.edu /Micro27/html/abst12.html (264 words)

	Real World Technologies - Intel's Next Generation Microarchitecture Unveiled
		Memory aliasing is a relatively easy to understand problem.
		Memory disambiguation is the process of determining whether a pair of memory instructions (usually a load and a store) alias, or share the same address.
		The problem is that to disambiguate a load, the memory system has to search the addresses of all in-flight store operations, which is hideously expensive.
	www.realworldtech.com /page.cfm?ArticleID=RWT030906143144&p=8 (393 words)

	Into the Core: Intel's next-generation microarchitecture: Page 8
		David Kanter's RWT article on Core cites research that demonstrates that over 97 percent of the memory accesses in a processor's instruction window fall into the B category, where the memory accesses are to unrelated locations and therefore theoretically could proceed independently of one another.
		Intel's memory disambiguation technology attempts to identify instances of false aliasing, so that in instances where the memory accesses are not aliased a load can actually execute before a store's destination address becomes available.
		In cases where Core's memory disambiguation algorithm guesses wrongly, the pipeline stalls and any operations that were dependent on the erroneous load are flushed and restarted once the correct data has been (re)loaded from memory.
	arstechnica.com /articles/paedia/cpu/core.ars/8 (1235 words)

	Compiler-Directed Dynamic Memory Disambiguation for Loop Structures (Site not responding. Last check: 2007-11-04)
		The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory.
		Thus, there may be several memory operations outstanding concurrently.
		However, the memory references must first be disambiguated in order to ensure correct execution of the program.
	csdl.computer.org /comp/proceedings/dsd/2004/2203/00/22030130abs.htm (220 words)

	Articles - Memory (disambiguation) (Site not responding. Last check: 2007-11-04)
		In biology and psychology, memory is the ability of a brain or nervous system to retain information.
		In a digital computer, memory is the part of the computer that retains data over time.
		Memories is the name of the first ending theme in One Piece (japanese TV version).
	www.1-ace.com /articles/Memory_%28disambiguation%29 (140 words)

	[No title]
		We evaluate a memory system design that can be both cost-effective as well as provide better performance, particularly for scientific workloads: a single level of (on-chip) cache backed up only by Joupi's stream buffers [10] and a main memory.
		While it is clear that shared memory machines are currently easier to program, in the future, programs will be written in high-level languages and compiled to the specific parallel target, thus eliminating this difference.
		The cost of memory structures with different sizes and associativities is estimated by using an established area model for on-chip memory.
	www.cs.wisc.edu /~arch/www/ISCAbib/isca21 (6592 words)

	An Overview of the Intel IA-64 Compile
		Similarly, moving memory references across function calls requires knowledge of what is modified or referenced by the function call.
		The compiler may disambiguate these two memory references either by determining that a and b are different memory objects or that field1 and field2 are non-overlapping fields.
		In general, in order to disambiguate this pair of memory references, the compiler must perform points-to analysis [12], which determines the set of memory objects that each pointer could possibly point to.
	developer.intel.com /technology/itj/q41999/articles/art_1e.htm (905 words)

	Sequence Disambiguation
		More precisely, Levy (1996) proposed that sequence coding by the hippocampus may be especially important when the sequences have overlapping elements through which memory of earlier elements must be remembered to complete each distinct sequence, a process called sequence disambiguation.
		However, it is not clear from this study whether the demand for disambiguation of sequences per se, rather than other aspects of spatial processing, is critical.
		In order to test whether sequence disambiguation is a fundamental feature of memory processing dependent on the hippocampus, we designed a sequence disambiguation task after Levy's (1996) formal model that involved two series of events that overlap in the middle items.
	www.bu.edu /cogneuro/research/lesions/seqdis.html (508 words)

	Intel Santa Rosa Does Not Support DDR2-800 » random process \| charlie 2.0
		The dual channel DDR2-667 memory controller provides a theoretical 10.67GB/s of memory bandwidth, which is, for almost all all intents and purposes, enough to saturate the CPU’s processing capability.
		Take a look at the AnandTech memory tests on the 965 Broadwater Core 2 platform (desktop version of Crestline) and you’ll see that even with the faster 1066MHz FSB, the difference between DDR2-667 and DDR2-800 is relatively minimal, in the range of 1% to 4%.
		Intel Smart Memory Access includes an important new capability called “memory disambiguation,” which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed.
	www.randomprocess.ca /2007/07/30/intel-santa-rosa-does-not-support-ddr2-800 (590 words)

	Compiler-Directed Dynamic Memory Disambiguation for Loop Structures
		The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory.
		This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single ported.
		However, the memory references must first be disambiguated in order to ensure correct execution of the program.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/dsd/2004/2203/00/2203toc.xml&DOI=10.1109/DSD.2004.1333268 (233 words)

	About the High-Level Optimizer (HLO) (Site not responding. Last check: 2007-11-04)
		The processor places the cache line into the cache, hoping that the code will subsequently request memory that is now sitting in cache.
		memory disambiguation—all memory references within the loop are unique.
		Because using HLO may cause the compiler to rewrite your algorithm, HLO is less safe than the -O2 option, and it may not improve performance for some programs.
	scv.bu.edu /SCV/Archive/linux-cluster/docs/intel_comp_docs_7.1/training/optimize/ch4/hloabout.htm (214 words)

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