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	Linux: Documenting Memory Barriers \| KernelTrap
		Memory barriers are a way of ordering IO accesses to devices from the kernel.
		I've rearranged the order of the sections, so that memory barriers are discussed in abstract first, and then described the memory barrier facilities available on Linux, before going on to more real-world discussions and examples.
		+ +What memory barriers are concerned with is controlling the order in which +accesses cross from the CPU side of things to the memory side of things, and +the order in which the effects are perceived to happen by the other observers +in the system.
	kerneltrap.org /node/6431 (6970 words)

	Linux Kernel Documentation :: memory-barriers.txt
		In the 95 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually 96 perform the memory operations in any order it likes, provided program causality 97 appears to be maintained.
		Memory barriers are used to 271 override or suppress these tricks, allowing the code to sanely control the 272 interaction of multiple CPUs and/or devices.
		335 336 A read barrier is a data dependency barrier plus a guarantee that all the 337 LOAD operations specified before the barrier will appear to happen before 338 all the LOAD operations specified after the barrier with respect to the 339 other components of the system.
	www.mjmwired.net /kernel/Documentation/memory-barriers.txt (4303 words)

	What is a "fence" ? - GameDev.Net Discussion Forums (Site not responding. Last check: 2007-10-26)
		Barrier in this instance is correctly described as a "fence" in the sense that it is an enclosure meant to restrict entry or exit from an area, in this case the area being a space in memory.
		Memory barriers are the key to lock-free threading semantics.
		Generally speaking, barriers are implemented as atomic operations on small addressible chunks of memory (such as a "word," a unit of storage that can be loaded and manipulated in a single CPU instruction).
	www.gamedev.net /community/forums/topic.asp?topic_id=419989 (952 words)

	The "Double-Checked Locking is Broken" Declaration
		Explicit memory barriers can be used to make it work in C++, but these barriers are not available in Java.
		This is completely legal under the existing Java memory model, and also legal in C and C++ (since neither of them have a memory model).
		On some processors, unless the processor performs a cache coherence instruction (e.g., a memory barrier), reads can be performed out of stale locally cached copies, even if other processors used memory barriers to force their writes into global memory.
	www.cs.umd.edu /~pugh/java/memoryModel/DoubleCheckedLocking.html (1942 words)

	DB2 UDB Information Zone
		Large memory support is critical for any database management system because simply put accessing data in memory is much faster than accessing it from disk storage.
		Removing the /3GB also reduces the DB2 UDB instance working set memory significantly which in turn provides very little memory space for both the database heap which is memory used to manage memory and the buffer pool windows which are used by the AWE API to map memory pages in and out of AWE memory.
		Memory affinity refers to pinning specific memory allocations in memory address space that is close to the processor utilizing the memory.
	www.tendigit.com /izone/briefs/memory.html (883 words)

	OpenVMS ask the wizard - Shared Memory, Threads, Interprocess Communicati
		When working with shared memory, you will want to be familiar with issues of read-write ordering, as well as with the necessity for use of memory barriers.
		Shared memory has programming considerations around read-write ordering and memory barriers -- with C, you can be using keywords such as volatile (which instructs the compiler to avoid caching values in registers), as well as the C asm directives and PALcode memory barrier (__MB) calls.
		For instance, your producer must issue a "memory barrier" instruction after writing the data to shared memory and before inserting it on the queue; likewise, your consumer must issue a memory barrier instruction after removing an item from the queue and before reading from its memory.
	h71000.www7.hp.com /wizard/wiz_2637.html (1064 words)

	The JSR-133 Cookbook
		Memory barriers are only indirectly related to higher-level notions described in memory models such as "acquire" and "release".
		And memory barriers are unrelated to the kinds of "write barriers" used in some garbage collectors.
		Memory barrier instructions directly control only the interaction of a CPU with its cache, with its write-buffer that holds stores waiting to be flushed to memory, and/or its buffer of waiting loads or speculatively executed instructions.
	gee.cs.oswego.edu /dl/jmm/cookbook.html (3944 words)

	OpenVMS ask the wizard - Shared memory and Alpha memory barriers (MB)?
		There are two general types of memory barrier, those that involve synchornizing completion of loads and stores to memory, and the IMB PALcode routine that must be used after modifications are made to the instruction stream.
		Memory barriers are also used to control how an Alpha processor aggregates memory writes -- an Alpha processor may cache a memory write for some relatively long interval, before actually completing the write to memory.
		If a memory barrier is required for a particular series of memory operations, explicitly include the memory barrier in the code.
	h71000.www7.hp.com /wizard/wiz_2681.html (1001 words)

	How Your Memory Works - MSN Encarta
		This is where you can work on improving your own memory processing to make sure you'll be able to retrieve a memory later.
		Mnemonics breaks this barrier of nature with a trick.
		Suppose I plan to give a speech about memory, beginning with examples of memory lapses, then going into the physiology of memory, and next dealing with the Greek invention of mnemonics.
	encarta.msn.com /encnet/departments/homework/?article=memorybetter (1075 words)

	MBR IT/.NET 247 : Memory barrier note on microsoft.public.dotnet.languages.csharp
		memory barriers are required for both read and write code paths.
		There is no memory barrier on this path.
		The memory barrier (AFAICT), flushes the cache on all processors.
	www.dotnet247.com /247reference/msgs/51/258796.aspx (2133 words)

	IBM PC compatible - Wikipedia, the free encyclopedia
		Users had to tolerate rebooting into DOS, fiddling with memory (see the 640k barrier) and reconfiguring their PC every time they wanted to load a game.
		For the first time, a PC programmer could benefit from Windows 95's memory management capabilities and extended functionality, and have API access to the graphics and sound cards - of which there were many versions and drivers.
		The processor speed and memory are many orders of magnitude greater than they were on the original IBM PC, yet any well-behaved program for the original IBM PC that does not call the hardware directly can still run on a modern PC.
	en.wikipedia.org /wiki/IBM_PC_compatible (4790 words)

	Linux Device Drivers, 2nd Edition: Chapter 8: Hardware Management
		These functions insert hardware memory barriers in the compiled instruction flow; their actual instantiation is platform dependent.
		The MIPS class of processors notwithstanding, directly mapped I/O memory is pretty rare in the current platform arena; this is especially true when a peripheral bus is used with memory-mapped devices (which is most of the time).
		We won't touch high ISA memory (the so-called memory hole in the 14 MB to 16 MB physical address range), because that kind of I/O memory is extremely rare nowadays and is not supported by the majority of modern motherboards or by the kernel.
	www.xml.com /ldd/chapter/book/ch08.html (7507 words)

	Programming Interfaces Guide
		The memory is allocated and aligned to contain an array of a specified number of elements of a specified size.
		The location in memory of the reallocated block might be changed, but the contents up to the point of the allocation size change remain the same.
		After a barrier open operation, failures of individual data access operations, both reads and writes, are not reported until the barrier close operation.
	docs.sun.com /source/806-4125/806-4125.book.xml (5956 words)

	LKML: David Howells: [PATCH] Document Linux's memory barriers [try #3] (Site not responding. Last check: 2007-10-26)
		+========================= + +Memory barriers are instructions to both the compiler and the CPU to impose an +apparent partial ordering between the memory access operations specified either +side of the barrier.
		They request that the sequence of memory events generated +appears to other components of the system as if the barrier is effective on +that CPU.
		It does _not_ guarantee that all +the memory accesses before the barrier will be complete by the time the barrier +itself is complete.
	lkml.org /lkml/2006/3/8/218 (2229 words)

	Nanoelectronics
		Misra is a recipient of a 2001 NSF Presidential Early Career Award for Scientists and Engineers—the highest honor given by the U.S. government to young scientists and engineers who show exceptional potential for leadership in their fields—for her work with silicon nanoelectronics.
		So instead of using silicon devices as memory storage elements, our team is using porphyrin molecules with functional properties that remain the same at any scale.” At only two nanometers across, these molecules can be much more densely and inexpensively packed on a chip.
		"The industry won't have to change much to use molecular materials in the memory portion of existing chip technology," he says, "and there appears to be no end to the demand for memory." With the worldwide market for computer chips at $35 billion and growing, both universities and ZettaCore's venture capital investors are beaming.
	www.ncsu.edu /research/results/vol3/memory.html (568 words)

	[PATCH] Document Linux's memory barriers [try #3]
		They request that the sequence of memory events gener ated +appears to other components of the system as if the barrier is effective on +that CPU.
		It does _not_ guarantee that all +the memory accesses before the barrier will be complete by the time the bar rier +itself is complete.
		+ +What memory barriers are concerned with is controlling the order in which +accesses cross from the CPU side of things to the memory side of things, an d +the order in which the effects are perceived to happen by the other observe rs +in the system.
	www.webservertalk.com /message1424732.html (2616 words)

	PowerPC storage model and AIX programming (Site not responding. Last check: 2007-10-26)
		The order in which memory accesses are performed may be different from both the program order and the order in which the instruction that caused the accesses are executed.
		The barrier created by the instruction will ensure that all accesses separated by the barrier are performed in the specified order, but accesses issued prior to the barrier might not be performed until long after the eieio instruction completes.
		Byte merging occurs when a sequence of individual memory writes are merged into a single word access, and it's not permitted if one of the bytes is accessed by more than one of the writes in the sequence.
	www.ibm.com /developerworks/eserver/articles/powerpc.html (6258 words)

	The Memory Management Glossary: B
		Hardware barriers don't require compiler support, and may be implemented on common operating systems by using memory protection.
		A memory barrier is an instruction on certain processor architectures that will ensure certain guarantees about the order of accesses to memory.
		Relevance to memory management: Bitmaps are sometimes used to represent the marks in a mark-sweep collector, or the used memory in a bitmapped fits allocator.
	www.memorymanagement.org /glossary/b.html (1808 words)

	Memory Ordering in Modern Microprocessors, Part II \| Linux Journal
		The first installment of this series was an overview of memory barriers, why they are needed in SMP kernels and how the Linux kernel handles them [August 2005].
		However, the stores to cacheable memory are ordered separately from the stores to non-cacheable memory, which, for example, means that eieio does not force an MMIO store to precede a spinlock release.
		MemIssue: complete preceding memory operations before subsequent memory operations, which is important for some instances of memory-mapped I/O. Lookaside: same as MemIssue but applies only to preceding stores and subsequent loads, and even then only for stores and loads that access the same memory location.
	www.linuxjournal.com /article/8212 (2648 words)

	ridiculous_fish » Blog Archive » Barrier
		The Alpha’s memory model guarantees so little that it is said to define the Linux kernel memory model - that is, the set of available barriers in the kernel source match the Alpha’s instruction set.
		Sometimes memory barriers are needed to guard against past or future reads and writes that occur in, say, the function that’s calling your function.
		Memory barriers are a faster, non-blocking, deadlock free alternative to locks.
	ridiculousfish.com /blog/archives/2007/02/17/barrier (4466 words)

	Great Barrier - Memory Alpha, the Star Trek Wiki
		The Great Barrier is an immense energy field that surrounds the core of the Milky Way Galaxy.
		Long believed to be impenetrable, the Enterprise-A successfully passed through the Great Barrier en route to the mythical planet of Sha Ka Ree.
		Although the events of The Final Frontier are riddled with mistakes, it is the official position of Paramount and the producers that Star Trek V: The Final Frontier is indeed considered canon.
	memory-alpha.org /en/wiki/Great_Barrier (192 words)

	[patch 4/9] blk: no memory barrier
		This memory barrier is not needed because the waitqueue will only get waiters on it in the following situations: rq->count has exceeded the threshold - however all manipulations of ->count are performed under the runqueue lock, and so we will correctly pick up any waiter.
		In this case, there is no additional help provided by the memory barrier.
		We are guaranteed to eventually wake up waiters because the request allocation mempool guarantees that if the mem allocation for a request fails, there must be some requests in flight.
	www.mail-archive.com /linux-kernel@vger.kernel.org/msg77643.html (144 words)

	Multimedia in the Windows Environment - B. The DOS memory barrier (Site not responding. Last check: 2007-10-26)
		The original IBM PC was based on the Intel 8088 processor, which is only capable of addressing 1 MB of memory (ie it only has sufficient internal "labels" for 1 MB).
		At that time this limitation was hypothetical because the first PC was provided with 64 Kb of RAM, so a theoretical limit of 640 Kb did not seem too low.
		This is the origin of the 640 Kb DOS memory "barrier", and the whole area of DOS memory management essentially consists of finding various ways around this limitation.
	ibis.nott.ac.uk /guidelines/ch14/chap1-4-B-4.html (143 words)

	LKML: David Howells: [PATCH] Fix memory barrier docs wrt atomic ops
		Fix the memory barrier documentation to attempt to describe atomic ops correctly.
		The possible offenders include: +Whilst they are technically interprocessor interaction considerations, atomic +operations are noted specially as some of them imply full memory barriers and +some don't, but they're very heavily relied on as a group throughout the +kernel.
		+[!] Note that special memory barrier primitives are available for these +situations because on some CPUs the atomic instructions used imply full memory +barriers, and so barrier instructions are superfluous in conjunction with them, +and in such cases the special barrier primitives will be no-ops.
	lkml.org /lkml/2006/4/5/28 (566 words)

	Fuzzy Acquires
		Operations dependent on the acquire must follow the memory barrier; however, operations independent of the acquire can now be inserted between the read and the memory barrier.
		Using fuzzy acquires has effectively increased the space between the acquire operation and its subsequent memory barrier operation and inserted useful computation from the previous iteration to overlap the latency of the acquire.
		Third, in a case with critical sections, if the independent computation added between the acquire read and the memory barrier is not completely overlapped, then the optimization may lengthen the critical section and increase subsequent acquire times.
	www-ece.rice.edu /~vijaypai/Asplos96/node19.html (534 words)

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