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Comparison of analytic performance models using closed mean-value analysis versus open-queuing theory for estimating ...   (Site not responding. Last check: 2007-10-07) Memory hierarchies typically contain translation directories, but they may or may not have to be included in the delay path, depending on the organization of the cache level. The application of queuing models to memory hierarchies has potential for improvement and is an area with substantial payoff as the complexity and design time of systems continue to increase and require continued refinement and improvement. The L1 cache is typically not included in the memory hierarchy analysis of a multiprocessor system because it is considered to be part of the processor. www.research.ibm.com /journal/rd/474/matick.html   (9809 words)

2 Memory Hierarchies   (Site not responding. Last check: 2007-10-07) Computer memories are built as hierarchies, with a series of different kinds of memories ranging from very fast, expensive, and therefore small memory at the top of the hierarchy, down to slow, cheap and very large memory at the bottom. It takes time to move between levels in the memory hierarchy, and moving is slower the farther down in the hierarchy one goes. First, the memory hierarchy is deeper, including both ``local memory'' and ``remote memory'' layers at the bottom (remote memory means memory physically on another processor). csep1.phy.ornl.gov /la/node2.html   (718 words)

Memory Hierarchies The memory hierarchy -- --- ------ --------- A. Since every instruction executed by the CPU requires at least one memory access (to fetch the instruction) and often more, the performance of memory has a strong impact on system performance. The basic idea, then, is to keep in the fastest memory in the hierarchy those data items that are being used currently, with the moderately fast memory used for items that will be needed soon and slow memory used for items that will not be needed until the distant future. Note that a memory hierarchy is based on a subset relationship - any information that is found in a higher level of the hierarchy is also found in all lower levels. www.math-cs.gordon.edu /courses/cs311/lectures-2003/memory_hierarchies.html   (5759 words)

Memory For various reasons, the memory cycle time is more than the speed of the memory chips (i.e., the length of time between succesive requests is more than the 80 ns speed of the chips in a small personal computer). Locality of reference can be exploited by implementing the memory as a hierarchy of memories, with each level of the hierarchy having characterisic access times and capacity. Hierarchical memories are complex, but efficient hardware algorithms that work in parallel with other processes to implement the replacement strategy mean that the fetch-decode-execute cycle time is not appreciably lengthened by the implementation of hierarchical memory. csep10.phys.utk.edu /guidry/phys594/lectures/performance_prog/memory.html   (760 words)

CS348C Final Report - Visualizing Memory Hierarchies Since the entire memory space is normally too big to fit on the screen, we decided to compact the addresses referenced by each program to eliminate the blocks of memory which the program did not use. Memory events (accesses, hits, misses, reads, writes, or memory delay) are plotted as bright bars which fade over time, allowing one to observe memory behavior trends over an adjustable period of time. When a memory event occurs, the height of the bar in the corresponding column is increased, and as time passes, the height of the bar decays at a user-adjustable rate. graphics.stanford.edu /~kekoa/classes/cs348c/aut96/project   (3924 words)

Is the Magic Number 7 Relevant to Web Page Design   (Site not responding. Last check: 2007-10-07) They found that memory span was not predictive of performance in any of the conditions, but that visual scanning was predictive of performance, especially in the deepest hierarchies. The 8x8x8 hierarchy, which had the longest reaction times, had the most time-outs (9 timeouts for 8x8x8, 2 for 16x32 and 3 for 32x16). Memory span scores had no correlation with reaction time in the 8x8x8 hierarchy, and poorer scanning ability correlated with faster performance in that hierarchy. research.microsoft.com /users/marycz/chi981.htm   (5472 words)

Home Page of Gurindar S. Sohi In the multiscalar arena, we continue to study memory systems to support multiscalar processing, support to allow the microarchitecture to span the multiscalar-multiprocessor spectrum, software optimizations and support for multiscalar processors, and ways of extracting multiscalar-specific information in a binary compatible manner. Whereas the instruction processing model has changed dramatically in the past decade, memory hierarchies have stayed pretty much the same for 2 decades. We are investigating alternate memory hierarchy organizations for the billion-transistor era. www.cs.wisc.edu /~sohi/research.html   (270 words)

OOPS Group Publications Worse, virtual memory experiments are limited in the number of variables and the range of those variables, as the time required to process a trace in simulation can be long. Dynamic memory allocation has been a fundamental part of most computer systems since roughly 1960, and memory allocation is widely considered to be either a solved problem or an insoluble one. Memory can thus only be used once per allocation/collection cycle, and a substantial amount of memory is both touched and dirtied at each cycle. www.cs.utexas.edu /users/oops/papers.html   (4948 words)

Issues in Compiler Research   (Site not responding. Last check: 2007-10-07) The increasing disparity between CPU and memory speeds over the past two decades has resulted in the use of multi-level memory hierarchies that attempt to exploit locality of reference in programs and hide memory latencies. The performance of many of today's complex applications is determined by the characteristics of the memory subsystem rather than by the operation count of the program, and there is often a dramatic difference between the peak advertised CPU performance and the observed performance of a given application. Intelligent prefetching of pages in a global memory environment[4] is an active area of operating systems research, but proceeds in a vacuum, as current techniques for predicting page reference patterns are very rudimentary. www.cs.unc.edu /~sc/research/NSF_position.html   (1722 words)

On Microprocessors, Memory Hierarchies, and Amdahl's Law   (Site not responding. Last check: 2007-10-07) The effect of increasing the clock rate without an accompanying increase in memory bandwidth is clearly indicated by the increase in speedup and the accompanying decrease in relative performance. The difference between the rates at which contemporary microprocessors can fetch words from memory and cache can be used in conjunction with an estimated (or targeted) performance figure to approximate the corresponding cache efficiency. In the mean time, larger caches, improved logic, and additional layers of memory hierarchy must serve to mask imbalances. archive.ncsa.uiuc.edu /Divisions/Communities/CSM/projects/success_stories/ASC_Amdahl.html   (831 words)

[No title]   (Site not responding. Last check: 2007-10-07) A choice of a cost-effective cluster computing platform for a given budget and for certain types of application workloads is mainly determined by its memory hierarchy and interconnection network of the cluster. The model covers the memory hierarchy of a single SMP, a cluster of workstations/PCs, or a cluster of SMPs by changing various modeling and architectural parameters. However, the interconnection network cost of a tightly coupled system with a short length of memory hierarchy, such as a SMP is significantly more expensive than a normal cluster network connecting independent computer nodes. www.cs.wm.edu /hpcs/WWW/HTML/publications/abs99-2.html   (265 words)

[No title]   (Site not responding. Last check: 2007-10-07) Abstract: Multilevel memory hierarchies are attractive from the point of view of cost-performance. This may be attributed to two factors: firstly, the page size (or the unit of information transfer between two levels) varies with the level in the hierarchy; secondly, the request streams that the lower (slower) levels see are the fault streams out of the immediately higher levels. An approximate technique is advanced for the characterization of the fault stream as a function of the request stream and the capacity of the level. www-db.stanford.edu /TR/CSL-TR-75-95.html   (217 words)

Flexible Memory-Hierarchy Simulator The determined data are used to configure a memory hierarchy simulator. The simulation of an unblocked matrix-matrix multiply with the memory hierarchy of an RS6000 shows a good correspondence of the calculated results with the measured execution. In this diploma-thesis, a simulator for memory hierarchies is presented that allows the calculation of execution times using the LDA-model. www.zib.de /schintke/ldasim/index.en.html   (508 words)

Effective Algorithms for Partitioned Memory Hierarchies in Embedded Systems Even though it is designed to handle a wide range of memory hierarchies, EMBARC is capable of generating partition assignments of similar quality to algorithms designed for specific memory hierarchies. A large range of benchmarks and memory models is used to demonstrate the effectiveness of the EMBARC algorithm. MPRES is an algorithm to estimate the effectiveness of the memory hierarchy for a given application without requiring time-consuming simulations. www.cs.virginia.edu /colloquia/event459.html   (299 words)

CS267: Notes for Lecture 2 (part 1), Jan 18, 1996 The significance of q is this: for each word read from slow memory (the expensive operation), one can hope to do at most q operations on it (on average) while it resides in fast memory. Another way to describe q is in terms of the miss ratio, the fraction of all memory references (to fast or slow memory) that ``miss'' the fast memory, and need data from the slow memory; a good problem has a low miss ratio. We will discuss matrix multiplication again later, for distributed memory parallel machines, where part of the algorithm design problem is to decide which processor memories store which parts of A, B and C, and which processors are responsble for computing which parts of the product A*B. http.cs.berkeley.edu /~demmel/cs267/lecture02.html   (2664 words)

Tech Report: HPL-1999-132: Automatic and Efficient Evaluation The performance of each processor is evaluated independent of its memory hierarchy, and each of the caches is simulated using the traces from a single reference processor. Since the changes in the processor architecture do indeed affect the address traces and thus the performance of the memory hierarchy, the overall performance is inaccurate. To overcome this error, the changes in the processor architecture are modeled as a dilation of the reference processor's address trace, where each instruction block in the trace is conceptually stretched out by the dilation coefficient. www.hpl.hp.com /techreports/1999/HPL-1999-132.html   (372 words)

An Analytical Model for Designing Memory Hierarchies Memory hierarchies have long been studied by many means: system building, trace-driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly size the different levels in a memory hierarchy to a first-order approximation. Another is that money spent on an n-level hierarchy is spent in a fixed proportion until another level is added. csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/trans/tc/&toc=comp/trans/tc/1996/10/txtoc.xml&DOI=10.1109/12.543711   (502 words)

ipedia.com: Java programming language Article   (Site not responding. Last check: 2007-10-07) In C++, memory must be allocated by the programmer to create an object, then deallocated to delete the object. Often a programmer forgets or is unsure when to deallocate, leading to a memory leak, where a program consumes more and more memory without cleaning up after itself. Memory leaks, however, can still occur if a programmer's code holds a reference to an object that is no longer needed—in other words, they still occur but at higher conceptual levels. www.ipedia.com /java_programming_language.html   (3740 words)

CS594: Notes for Lecture 5, Feb 11, 1998 On the RS6000, when data is fetched from slow memory to fast memory (cache), it comes in 256 byte chunks called cache lines, and a good algorithm will use all this data at the same time, to minimize the number of times the cache line has to be fetched from slow memory. The cache is the second level in the memory hierarchy of the RS6000/590, and the Data Cache Unit (DCU) manages data movement between the cache and the third level in the hierarchy, which is main memory. This is called a write-back policy, since slow memory is updated only when a dirty cache line is evicted, in contrast to a write-through policy, where slow memory is updated on every write (this is slower, since it accesses slow memory more often). www.cs.utk.edu /~dongarra/WEB-PAGES/lect05.html   (5624 words)

Compiler-directed Data Prefetching in Multiprocessors with Memory Hierarchies - Gornish, Granston, Veidenbaum ...   (Site not responding. Last check: 2007-10-07) Abstract: Memory hierarchies are used by multiprocessor systems to reduce large memory access times. It is necessary to automatically manage such a hierarchy, to obtain effective memory utilization. In this paper, we discuss the various issues involved in obtaining an optimal memory management strategy for a memory hierarchy. citeseer.lcs.mit.edu /42264.html   (638 words)

The Impact of Memory Hierarchies on Cluster Computing   (Site not responding. Last check: 2007-10-07) A choice of a cost-effective cluster computing platform for a given budget and for certain types of application workloads is mainly determined by its memory hierarchy and interconnection network of the cluster.Finding such a solution from exhaustive simulations would be highly time-consuming and expensive; and predictions from measurements on existing clusters would be impractical. The model has been validated by simulations.Our study shows that the length of memory hierarchy is the most sensitive factor to affect the execution time for many types of workloads. However, the interconnection network cost of a tightly coupled system with a short length of memory hierarchy, such as an SMP is significantly more expensive than a normal cluster network connecting independent computer nodes. csdl.computer.org /comp/proceedings/ipps/1999/0143/00/01430061abs.htm   (350 words)

The Effect Of Conceptual Hierarchies On Memory Recall Below is a short sample of the essay "The Effect Of Conceptual Hierarchies On Memory Recall". If you sign up you could be reading the rest of this essay in under two minutes. For a true insight into someone's memory the participant has to be receptive at the time of testing. www.coursework.info /i/68919.html   (679 words)

Citations: Some issues and strategies in heap management and memory hierarchies - Paul, March (ResearchIndex) Exact Positioning of Data Approach to Memory Mapped Persistent.. The criterion used to judge the success of this approach is whether an independent facility for storage management can provide performance that is close to traditional schemes that incorporate storage management directly with the data structure. Memory Organization In the EPD approach, memory is.... citeseer.ist.psu.edu /context/343160/0   (762 words)

Publications   (Site not responding. Last check: 2007-10-07) We propose several modifications to the binary buddy system for managing dynamic allocation of memory blocks whose sizes are powers of two. The standard buddy system allocates and deallocates blocks in Theta(lg n) time in the worst case (and on an amortized basis), where n is the size of the memory. The first scheme uses just one more word of memory than the standard buddy system, but may result in greater fragmentation than necessary. www.daimi.au.dk /~gerth/pub6.html   (256 words)

Optimal Deterministic Sorting on Parallel Processors and Parallel Memory Hierarchies   (Site not responding. Last check: 2007-10-07) ``Optimal Deterministic Sorting on Parallel Processors and Parallel Memory Hierarchies,'' submitted for publication. We present a practical deterministic load balancing strategy for distribution sort that is applicable to parallel disks and parallel memory hierarchies with both single and parallel processors. The algorithms so derived are optimal for all parallel memory hierarchies with any type of a PRAM base-level interconnection and are either optimal or best-known for a hypercube interconnection. www.cs.duke.edu /~jsv/Papers/catalog/node16.html   (189 words)

OOPS Research Group (U of Texas at Austin) Other work on high-performance memory managers can be found on Emery Berger's page. Memory hierarchies, especially persistent object stores, virtual memories, and caches. Basic studies of program behavior and memory allocation, which attempt to repair the damage done by three decades of mostly unsound studies of memory allocation. www.cs.utexas.edu /users/oops   (520 words)

CS 8803, Memory Hierarchies and Program Locality The difference in speed between processors and main memory keeps growing. The difference in speed between silicon memory and magnetic devices (i.e., disks) is also growing. In this course we will examine research ideas and directions relating to memory hierarchies (cache, virtual memory, etc.) as well as memory management (allocators and garbage collection). www.cc.gatech.edu /%7Eyannis/fall00   (343 words)

Memory Hierarchies & Storage Devices   (Site not responding. Last check: 2007-10-07) The Memory Hierarchy is based upon speed of access. However, this speed comes with a price tag attached which varies inversely with the access time of memory. Like cars the faster the memory access is the more it costs. www.cs.uwm.edu /classes/cs557/chapter5/sld003.htm   (39 words)

mhm   (Site not responding. Last check: 2007-10-07) Applications that process huge datasets have to take into account that there is a memory hierarchy of caches, local memory, non-uniform shared or distributed memory and disks. Furthermore, new hierarchy levels like third level cache, NUMA, or clusters of SMPs are becoming wide spread. Submissions are welcome on topics related to memory hierarchies. pdp2003.ima.ge.cnr.it /mhm.htm   (132 words)

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