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Topic: Memory locality

	Garbage Collection Techniques to Enhance Memory Locality in Java Programs
		Dynamic memory allocation and GC often have negative effects on the placement of data in memory, and, therefore, the memory locality properties.
		On modern systems, memories are organized in a hierarchy, from the top of the pyramid, the small and fast memory, to the bottom, the larger and slower memories, i.e.
		As memory allocation and GC are critical to memory management and the locality, we think this research would be of valuable significance in improving system performance for Java programs (and possibly other object oriented languages).
	pages.cs.wisc.edu /~zhong/hilldale_proposal.html (1710 words)

	CmpSci 535 Lecture 9
		The memory hierarchy is viable because programs tend to exhibit a property known as locality.
		The hit ratio is an important measure of the performance of a memory level and is the probability that a reference is to a value already in a given level of the hierarchy.
		Memory accesses can be pipelined so that the rate of data transfer is maintained, but when loads or stores occur in isolation and there are no independent operations to fill the resulting delay, then the CPU sees a memory wait state and is effectively slowed down by the mapping.
	www.cs.umass.edu /~weems/CmpSci535/535lecture9.html (6611 words)

	Garbage Collection Techniques to Enhance Memory Locality in Java Programs
		Dynamic memory allocation and GC often have negative effects on the placement of data in memory, and, therefore, the memory locality properties.
		On modern systems, memories are organized in a hierarchy, from the top of the pyramid, the small and fast memory, to the bottom, the larger and slower memories, i.e.
		As memory allocation and GC are critical to memory management and the locality, we think this research would be of valuable significance in improving system performance for Java programs (and possibly other object oriented languages).
	www.cs.wisc.edu /~zhong/hilldale_proposal.html (1710 words)

	Performance Tuning for the Origin2000 (Site not responding. Last check: 2007-10-12)
		Namely, 90% of each process's cache misses are from memory accesses to an almost unshared section of memory, 5% to a section of memory shared with another process, and the remaining 5% to a section of memory shared with a third process.
		Applications with modest memory requirements are likely to succeed in allocating all their memory from the node on which they run.
		The memory locality management automatically performed by IRIX means that most Origin users will be able to achieve good performance and enhanced scalability without having to program any differently than they do an a Power Challenge.
	www.gre.ac.uk /~lp01/sgi/origin2000tut/O2000Tuning.2.html (3855 words)

	SGI TPL (IRIX 6.5: Developer/OrOn2_PfTune - Chapter 2. SN0 Memory Management)
		If IRIX paid little attention to memory locality, the program could end up in the situation shown in Figure 2-3: two processes and half the memory in one corner of the machine, the other processes and memory running in an opposite corner.
		Memory locality domain sets describe how a program's MLDs should be placed within the machine, and whether they need to be located near any particular hardware devices (for example, close to a graphics pipe).
		If the initialization of memory is done in parallel in each process, each CPU is the first to touch its 90% piece and the two adjacent 5% pieces, causing those segments to be allocated locally.
	techpubs.sgi.com /library/tpl/cgi-bin/getdoc.cgi?coll=0650&db=bks&srch=&fname=/SGI_Developer/OrOn2_PfTune/sgi_html/ch02.html (4337 words)

	How does Cache memory effect the system
		There are several sorts of locality, but we mainly mean that the same data are often used several times, with accesses that are close together in time, or that data near to each other are accessed close together in time.
		The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations.
		As long as most memory accesses are to cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
	www.memory.bz /cache-memory/cpu-cache-memory.html (232 words)

	Issues Related to Cache Memory (Site not responding. Last check: 2007-10-12)
		Spatial locality: Memory items (instructions or data) in a few localized areas of the memory (program or data structure) are more frequently referenced than other areas.
		Temporal locality: Memory items that are recently referenced are more likely to be referenced soon than those which have not been referenced for a longer time.
		When the CPU needs to read a word from the memory, the block containing the word is brought from MM to CM, while at the same time the word is forwarded to the CPU.
	jingwei.eng.hmc.edu /~rwang/e85/lectures/memory/node3.html (317 words)

	Memory Locality (Site not responding. Last check: 2007-10-12)
		Data is transferred between cache and memory in a block transfer operation, which is the optimal way of exploiting available bandwidth, but may take many clock cycles to perform the transfer.
		Just as the cache exists in relation to main memory, memory is in turn related to virtual memory.
		If there is no room in memory for the page, the page in memory that was accessed furthest in the past is written out to disk, and then replaced by the incoming page.
	www.ac3.edu.au /hpc-intro/node9.html (642 words)

	Memory Placement Optimization (MPO) (Site not responding. Last check: 2007-10-12)
		Memory locality effects depend in large part on latency and bandwidth.
		Latency measures the speed in which data can be brought from memory to the processors, and the bandwidth measures how much data can be moved in a certain interval.
		MPO in Solaris optimizes for performance through latency and bandwidth, attempting to ensure that memory is as close as possible to the processors that access it, while still maintaining enough balance within the system to avoid the introduction of bottlenecking hotspots.
	iforce.sun.com /protected/solaris10/adoptionkit/general/features/mpo.html (407 words)

	URCS Systems Technical Reports
		The design of the memory hierarchy in a multi-core architecture is a critical component since it must meet the capacity (in terms of bandwidth and low latency) and coordination requirements of multiple threads of control.
		Locality is an important property for today's machines, because it hides the relatively high latency of computer memories.
		Most of the optimization techniques for enhancing locality and reducing false sharing have been proposed in the context of numeric applications involving array-based data structures, and are not applicable for dynamic data structures due to dynamic memory allocation from the heap with arbitrary addresses.
	www.cs.rochester.edu /trs/systems-trs.html (17675 words)

	Slava Oks's WebLog : Platform layer for SQL Server:
		Memory sharing can be described as memory or residence affinity and represents memory locality.
		Having local storage at the node level enables developers to have local state per node as well as to partition global state across nodes.
		Requirements for API design were conflicting: we had to hide locality awareness as much as possible from high level developers and at the same time enable powerful developers to exploit capabilities of the underneath hardware up to its limits.
	blogs.msdn.com /slavao/articles/441058.aspx (4354 words)

	Improving the Cache Locality of Memory Allocation - Grunwald, Zorn, Henderson (ResearchIndex)
		Improving the Cache Locality of Memory Allocation - Grunwald, Zorn, Henderson (ResearchIndex)
		Rarely do programmers concern themselves with details of memory allocators; most assume that memory allocators provided by the system perform well.
		This paper presents a performance evaluation of the reference locality of dynamic storage allocation algorithms based on trace-driven simulation of five large allocation-intensive C programs.
	citeseer.ist.psu.edu /grunwald93improving.html (690 words)

	Issues in Compiler Research
		The increasing disparity between CPU and memory speeds over the past two decades has resulted in the use of multi-level memory hierarchies that attempt to exploit locality of reference in programs and hide memory latencies.
		The performance of many of today's complex applications is determined by the characteristics of the memory subsystem rather than by the operation count of the program, and there is often a dramatic difference between the peak advertised CPU performance and the observed performance of a given application.
		Intelligent prefetching of pages in a global memory environment[4] is an active area of operating systems research, but proceeds in a vacuum, as current techniques for predicting page reference patterns are very rudimentary.
	www.cs.utexas.edu /ftp/pub/new_directions/new_sid_chatterjee.html (1722 words)

	Method and system for improving the locality of memory references during execution of a computer program - Patent ...
		Virtual memory refers to a set of techniques that provide a logical address space that is typically larger than the corresponding physical address space of the computer system.
		One of the primary benefits of using virtual memory is that it facilitates the execution of a program without the need for all of the program to be resident in main memory during execution.
		To the extent that unrequired code portions are loaded into memory by this process, valuable memory space is wasted, and the total number of pages loaded into memory is much larger than necessary.
	www.freepatentsonline.com /5664191.html (7164 words)

	System Flexibility
		Through examples, we present several hypothetical ways in which Jupiter could be modified to exploit memory locality on a non-uniform memory access (NUMA) multiprocessor system.
		In such a system, accessing local memory is less time-consuming than accessing remote memory.
		At the implementation level, Java objects are composed of two resources: memory to store field data, and a monitor to synchronize accesses to this data.
	www.usenix.org /events/jvm02/full_papers/doyle/doyle_html/node3.html (540 words)

	Haverford College Computer Science (Site not responding. Last check: 2007-10-12)
		I am investigating techniques for transforming the mapping of values to memory locations as a way of improving cache hit ratios.
		This work differs from other work on improving cache performance for regular scientific programs because of its focus on finding and exploiting scalable locality (locality that can be made to grow with the size of the problem).
		We have demonstrated that time skewing can be beneficial for current architectures, and that it can compensate for machines in which non-local references are extremely expensive (for example, we have obtained speedups ranging from a factor of 27 to a factor of 490 for programs that use data sets too large to fit in RAM).
	www.cs.haverford.edu /people/davew/tskew.html (170 words)

	Coping with Memory Locality - Dynamic Data Migration (Site not responding. Last check: 2007-10-12)
		A cache was kept in local memory on the BBN systems to minimize retrieving a portion of space from global memory more than once.
		The number of local neighbors drops as the number of processors is increased.
		Because of the shared uniform memory these runs were run with helping (load sharing) enabled but with data migration disabled.
	www.netfact.com /crs/papers/thesisold/rvi (4091 words)

	Time Skewing: A Value-Based Approach to Optimizing for Memory Locality - McCalpin, Wonnacott (ResearchIndex) (Site not responding. Last check: 2007-10-12)
		Abstract: As the gap between processor and main memory speed continues to grow, higher cache hit rates are required for efficient processor use.
		Time skewing: A value-based approach to optimizing for memory locality.
		210 Strategies for cache and local memory management by global p..
	citeseer.lcs.mit.edu /mccalpin99time.html (566 words)

	sgsa (Site not responding. Last check: 2007-10-12)
		In light of contemporary political, social and cultural transformations the issues of space, place, locality and memory pertain more than ever to the ongoing discussion about personal/regional/national identities.
		The way we remember our past and our heritage inscribes the space we live in: places we remember and those we wish to forget, monuments we pull down and erect and museums we build are only some of the signposts on the landscape our cultural memory.
		We invite contributors from various areas (literature, visual arts, film, sociology, philosophy, cultural studies, urban studies) to explore dimensions of space(s), places, locality and memory in their respective disciplines.
	www.arts.ualberta.ca /SGSA/space3.htm (180 words)

	Time Skewing: A value-based approach to optimizing for memory locality (Site not responding. Last check: 2007-10-12)
		Loop skewing has generally been overlooked in other work on compile-time optimization for locality (such as that by McKinley, Carr, and Tseng), largely due to the fact that empirical studies by Wolf and Lam found that it was not useful in practice.
		However, as we show in a short communication (gzipped) we recently submitted to ACM TOPLAS, the value of loop skewing may only be apparent when combined with transformations not implemented by Wolf and Lam.
		Tina has extended the code generation system in the Omega Library to perform automatic code generation involving memory mapping as well as iteration space remapping.
	www.haverford.edu /cmsc/davew/cache-opt/cache-opt.html (322 words)

	[No title] (Site not responding. Last check: 2007-10-12)
		Abstract With the falling price of the memory, an increasing number of multimedia servers and proxies are now equipped with a large DRAM memory space.
		The running buffer approach and its alternatives are representative techniques to cache streaming data in the memory.
		Considering user access patterns and characteristics of the requested media objects, our techniques adaptively allocate memory buffers to fully utilize the currently buffered data of streaming sessions, with the aim to reduce both the server load and the network traffic.
	www.cse.ohio-state.edu /hpcs/WWW/HTML/publications/abs04-4.html (247 words)

	11.3.2.2 Cache memory (Site not responding. Last check: 2007-10-12)
		Based on the principle of locality, cache memory can be an effective way to increase the memory access speed.
		Whether to use cache or not depends on whether the principle of locality is satisfied.
		When the Harvard architecture is adopted in a system, one may use cache memory for program memory and not for data memory.
	www.engr.iupui.edu /~skoskie/EE362/lecture_notes/LNC04_html/text17.html (215 words)

	Exploiting Memory Bank Locality in Multiprocessor SoC Architectures (Site not responding. Last check: 2007-10-12)
		One way of alleviating this power problem is to divide the off-chip memory into multiple banks, each of which can be power-controlled independently using low-power operating modes.
		This is achieved by ensuring bank locality, which means that each processor localizes its accesses into a small set of banks.
		Our results show that the proposed solution improves bank locality significantly, and reduces the overall memory system energy consumption by up to 34% over a strategy that makes use of the low-power modes but does not employ our strategy.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/ipdps/2004/2132/01/2132toc.xml&DOI=10.1109/IPDPS.2004.1303037 (350 words)

	25 Nuttall (Site not responding. Last check: 2007-10-12)
		In an increasingly globalized world, local understandings of place, locality and belonging are threatened by national, political and economic interests.
		In Greenland, locality remains an important marker of individual and community identity, but debates about the nature of Greenlandic identity centre increasingly on the relationship between local identity and national identity.
		Drawing upon ethnographic material from south Greenland, the article demonstrates that local identities remain strong, as do the bonds between people and place, but that the process of Greenlandic nation-building threatens to dispossess people living in small communities from their customary rights of access to local resources.
	www.fss.ulaval.ca /etudes-inuit-studies/v25te02.HTML (446 words)

	Memory Locality (Site not responding. Last check: 2007-10-12)
		Larger applications having the property of data locality, ie sequential data acesses are near to each other in address space, will have a high cache hit to miss ratio, will also be quite efficient.
		So, if your vector data is arranged so that each element is next to eac other, you will be using all memory banks.
		When you include this, and the fact that modern CPUs may actually contain 2 or 3 levels of cache, you get a memory heirarchy, with the CPU's registers at the top (immediate access, scarce resource) down to tape (very high latency, but vast resources) at the bottom.
	parallel.hpc.unsw.edu.au /rks/docs/hpc-intro/node8.html (646 words)

	Virtual Memory Locality Java Workbench (Site not responding. Last check: 2007-10-12)
		Simulations of program behavior show that during process time, a program will exhibit phases (periods of little change in the contents of main memory) alternating with transitions (periods of significant change in the contents of main memory).
		The principle of locality states that during phases of execution, a program requires a small subset of virtual pages.
		The set of pages used during a phase is the "locality set" of that phase.
	cne.gmu.edu /workbenches/local/local.html (214 words)

	One Processor: blocking of data to increase locality of memory access (Site not responding. Last check: 2007-10-12)
		One Processor: blocking of data to increase locality of memory access
		A single large block causes performance to depend strongly on view direction.
		The optimal block size is between 0.5 and 1.0 times the size of the L2 cache.
	www.mepalmer.net /writing/prs97-slides/html/sld014.htm (50 words)

	Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics (Site not responding. Last check: 2007-10-12)
		As the size of reconfigurable fabrics increases we can envision entire applications being mapped to a reconfigurable device; not just the code, but also the memory.
		In this paper we explore how mobile memory techniques, inspired by cache-only memory architectures, can be applied to help solve this problem.
		The basic idea is to move the memory to the location of the accessor.
	csdl2.computer.org /persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/fccm/2002/1801/00/1801toc.xml&DOI=10.1109/FPGA.2002.1106674 (206 words)

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