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Topic: Memory refresh

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	2K vs 4K Refresh
		Internally, computer memory is arranged as a matrix of "memory cells" in rows and columns, like the squares on a checkerboard, with each column being further divided by the I/O width of the memory chip.
		Refresh is the process of recharging, or re-energizing, the cells in a memory chip.
		Refresh rate is determined by the total number of rows that have to be refreshed in a memory chip.
	www.oempcworld.com /support/2K_vs_4KRefresh.htm (1134 words)

	Volatile memory - Wikipedia, the free encyclopedia
		Volatile memory, or volatile storage, is computer memory that requires power to maintain the stored information, unlike non-volatile memory.
		Most forms of modern random access memory are volatile storage, including dynamic random access memory and static random access memory.
		Content addressable memory and dual-ported RAM are usually implemented using volatile storage.
	en.wikipedia.org /wiki/Volatile_memory (94 words)

	U.S. Patent: 5184325 - Dynamic associative memory with logic-in-refresh - February 2, 1993
		The memory is organized within the chip as a 512 row, 2048 bit-per-row memory in which an entire 2048 bit row is read, one after another, in each refresh cycle.
		As noted earlier, a refresh cycle is a period of time required to refresh one bit of one column with one sense amplifier, and is performed simultaneously for each column in the memory.
		At the beginning of a refresh operation, dual-rank flip-flops P1 and P3 are initialized to zero, and early in a refresh cycle, flip-flop P3 is loaded with the exclusive-OR of all eight data bits which are read from memory along with the old value of P3.
	www.everypatent.com /comp/pat5184325.html (6178 words)

	Dual purpose screen/memory refresh counter - United States Patent 4,648,032
		An image memory system according to claim 9 wherein said third pair of inputs further comprises means for identifying said address bit as a row address bit when said means is in a first state, said means identifying said address bit as a column address bit when said means is in a second state.
		To insure that all of the memory cells within a RAM remain sufficiently refreshed, all of the rows in the RAM must be refreshed on a periodic basis.
		The row addresses used to refresh the RAM are generated by an X refresh counter which counts bit strings for each horizontal line on the display screen; and, by a Y refresh counter which counts the number of completed horizontal lines on the display; and, by an interlacing flip/flop.
	xrint.com /patents/us/4648032 (3381 words)

	Microcode-controlled memory refresh apparatus for a data processing system - Patent 4218753
		refresh address gating means for receiving said successive memory refresh address signals and responsive to said refresh gate signals to provide said memory refresh signals to said dynamic memory means upon occurrence of said each one of said certain of said microinstructions to refresh said successive portions of said dynamic memory means.
		The memory refresh means of claim 1 and wherein said first counter means includes counter preset means for adjusting maximum count of said first counter means to select the duration of said first certain time intervals if frequency of said timing pulses provided by said system clock means is changed.
		In a further feature of the present invention wherein the memory is constructed from MOS technology and comprises a plurality of memory locations, and wherein the physical quantity representation of the binary data is voltage stored on inherent capacitance in the MOS memory, the refreshing apparatus comprises first and second counter circuits.
	www.freepatentsonline.com /4218753.html (10338 words)

	Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral ...
		As further illustrated, the memory refresh cycles continue to occur on a periodic basis and typically utilize a memory cycle that would be otherwise allocated to the peripheral controller.
		After the memory refresh cycle is completed, the system memory refresh circuit 330 returns the REFREQ signal on the refresh request line 376A to its inactive state to indicate to the bus arbitration control circuit 370 that the shared bus 318 is available.
		During the refresh cycle, the BUS MASTER A 350 retains an active signal on the BUSREQA line 380A to indicate that it was not finished with its transfers and that the control of the shared bus 318 should be returned to it when the refresh cycle is completed.
	www.freepatentsonline.com /5438666.html (14071 words)

	Random Access Memory (RAM)
		Although a row of cells is refreshed during a read or write, the randomness of memory references cannot guarantee that every word in a memory module is refreshed within the 2-ms time limit.
		In a memory refresh cycle, a row address is sent to the memory chips, and a read operation is performed to refresh the selected row of cells.
		During a memory refresh cycle, all memory chips are enabled so that memory refresh is performed on every chip in the memory module simultaneously.
	www.electronics.dit.ie /staff/tscarff/memory/ram.htm (1008 words)

	Refresh Rates and Interlacing
		The refresh rate is the number of times per second that the RAMDAC is able to send a signal to the monitor and the monitor is able to repaint the screen.
		The refresh rate necessary to avoid this varies with the individual, because it is based on the eye's ability to notice the repainting of the image many times per second.
		The refresh rate is related directly to the resolution of the image--higher resolution images generally have lower refresh rates.
	www.pcguide.com /ref/video/modesRefresh-c.html (1038 words)

	Memory parity errors: Causes and suggestions
		One of the memory chips is being affected by "cell leakage." This ends up being a true parity error and is also known as a "soft error." This occurs when the change in the state of an individual cell (a zero or one) electrically leaks into a neighboring cell changing it's state.
		When the memory is read back, it no longer matches the parity bit's checksum value and an NMI is issued to the processor signaling a parity error has occurred.
		If you add more memory to the system, it is possible that the BIOS will recognize the full amount of physical RAM that is installed in the server but that Windows will recognize only a part of the RAM.
	support.microsoft.com /?kbid=101272 (1222 words)

	Computer Dictionary-Glossary-Computer Memory-PC Meomies-RAM-SDRAM-Best Computer Online Store Houston Buy Discount ...
		Refreshing is done by reading every "row" in the memory chip one row at a time; the process of reading the contents of each capacitor re-establishes the charge.
		A specific procedure is used to control each access to memory, which consists of having the memory controller generate the correct signals to specify which memory location needs to be accessed, and then having the data show up on the data bus to be read by the processor or whatever other device requested it.
		Memory Packaging - Like processors, memory is made from tiny semiconductor chips and must be packaged into something less fragile and tiny in order to be integrated with the rest of the system.
	www.directron.com /gloscommem.html (7754 words)

	What is DRAM
		The memory cells are arranged in rows and columns.
		The memory cells arranged in rows are called word lines and the memory cells that are arranged in the columns are called bit lines.
		A DRAM memory cell is a capacitor that is charged to produce a 1 or 0.
	www.faculty.iu-bremen.de /birk/lectures/PC101-2003/08dram/Principles/DRAM02.htm (655 words)

	Rule 612.Writing Used to Refresh Memory.
		Alaska Rule of Civil Procedure 43(g) (9), superseded by this rule, allowed materials to be used to refresh the recollection of a witness on the stand only if they were written by the witness himself or under his direction at a time when the fact was fresh in his memory.
		This section outlines the proper procedure for handling material used to refresh recollection that is to be made available to a party for impeachment use.
		If the prosecutor should refuse to disclose writings or objects used to refresh the witness' recollection despite a finding that disclosure is required in the interests of justice, dismissal may be the only appropriate remedy.
	www.touchngo.com /lglcntr/ctrules/evcom/EVC-47.htm (1158 words)

	Advanced Chipset Setup
		Hidden Refresh: Allows the RAM refresh memory cycles to take place in memory banks not used by your CPU at this time, instead or together with the normal refresh cycles, which are executed every time a certain interrupt (DRQ0 every 15 ms) is called by a certain timer (OUT1).
		Since memory is accessed ALL of the time it is easy to synchronize the refresh on the falling edge of this event.
		Hi-speed Refresh: Refreshes are occurring at an higher frequency, which is improving the system performance.
	burks.bton.ac.uk /burks/pcinfo/hardware/bios_sg/advchip.htm (3409 words)

	Memory Devices
		This type of memory is the kind most of us probably think of when talking about how much memory is available.
		Random access memory (RAM) is the kind of memory used to hold programs and data when a processor is active.
		This is the type of memory used to keep the time in a VCR, and stores your favorite stations on the radio in your car, and keeps your BIOS settings for you computer.
	www.bamafolks.com /~randy/students/embedded/memory.html (2078 words)

	Fastest way of Database Access : Caching Records in Memory
		Once this time period expires, the data in cache is refreshed with fresh content from the database (or whatever data source).
		Notice that when content is displayed from memory it takes 0 ms and when content is refreshed from database, it takes on average 30 ms.
		After the page was refreshed, it displayed the list from the cache, see the status message at top left changing, also keep an eye on the time elapsed pointer at the bottom.
	www.stardeveloper.com /articles/display.html?article=2001080501&page=1 (996 words)

	Portable Design - Mobile RAMs can help save power (Site not responding. Last check: 2007-10-29)
		In addition to lowering the operating voltage, power can be saved by optimizing the memory's refresh cycle to account for variations in the ambient temperature, and by allowing only necessary portions of the memory to be refreshed.
		The Mobile RAM reduces this unnecessary power consumption by refreshing only a defined portion of the memory, using a PASR (partial-array self-refresh) capability that recharges the cells in a pre-selected memory segment and discards the contents of the other cells.
		But because all memory data is lost in this mode, it's intended primarily for use in a limited number of applications, none of which includes long-term data storage.
	pd.pennnet.com /Articles/Article_Display.cfm?Section=Archives&Subsection=Display&ARTICLE_ID=149778&KEYWORD=MEMORY (1215 words)

	How memory works
		RAS refresh is accomplished by sequentially addressing the row addresses and enabling the RAS signal which causes every memory cell in the row to refresh.
		When a memory location is written to, a hardware parity generator generates a parity bit that is stored in an extra memory chip.
		One limiting factor is the memory cell where stray capacitance in data lines slows the bus down - so look for the trend to a system module where the RAM die and processor are paced in a cartridge as is the Pentium II is with it's cache memory.
	www.xtronics.com /memory/how_memory-works.htm (4108 words)

	Memory (Site not responding. Last check: 2007-10-29)
		In memory industry, there are a few technologies being developed in university lab or giant players like Intel.
		Scott, a research scientist from IBM lab in San Jose, recently wrote an article that is published on Science [1] to highlight the qualification for promising memory that is based on resistively changing for writing (or erasing) data.
		Further, a classical trap theory proposed by Simmons [2] is applied to explain the memory behavior observed in the device.
	www.odcad.com /ChangingContents/DevicePhysics/Memory/DevicePhysics_Memory.html (1699 words)

	Refresh system for dynamic RAM memory (US4249247)
		A method and apparatus for controlling the refreshing of a volatile memory is disclosed in which conflicts between a memory refresh operation, the requirements for access to the memory during a data processing operation and a power up or power down condition are resolved.
		When a conflict occurs, clock signals are generated to provide a contention refresh operation of the memory with minimum interruption to normal access time between the control processor and the memory.
		means operatively coupled to said memory unit for selecting and enabling either of said refreshing means or said processing unit access to said memory unit in response to the generation of said memory access signal or said first periodic refresh control signals;
	www.delphion.com /details?pn10=US04249247 (292 words)

	MicroMac 168-pin 5V EDO Memory DRAM DIMM with parity
		Part of the 168 connections are the 64 data bits that are transferred to and from the memory module.
		Some incompatible memory chips are offered with 4K refresh, but some Mac models require 2K-refresh or less to function reliably.
		In order to successfully upgrade the memory of your Mac, there is no need to understand all these terms in detail.
	www.micromac.com /products/memory_dimm_168pin_parity.html (641 words)

	refresh definition - Dictionary - MSN Encarta
		Search for "refresh" in all of MSN Encarta
		re·fresh (past and past participle re·freshed, present participle re·fresh·ing, 3rd person present singular re·fresh·es)
		transitive verb reactivate memory: to prompt or reactivate the memory with a piece of information
	encarta.msn.com /encnet/features/dictionary/DictionaryResults.aspx?refid=1861700258 (155 words)

	Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral ...
		a first input connected to receive a refresh request signal from said memory refresh control circuit, said memory refresh control circuit activating said refresh request signal when said memory refresh control circuit wants control of said shared bus to refresh said system memory;
		a second output connected to provide a refresh grant signal to said memory refresh control circuit, said bus arbitration control circuit activating said refresh grant signal to inform said memory refresh control circuit that it has control of the shared bus;
		said logic sequencer responsive to an active hold acknowledge signal from said microprocessor when said memory refresh circuit is maintaining an active refresh request signal to activate said refresh grant signal to grant control of said shared bus to said memory refresh circuit,
	www.delphion.com /details?pn10=US04987529 (894 words)

	Refresh my memory on... - Fly Fishing Utah - The Utah Fly Fishing Resource
		The closure of the Lower Provo in the late 80's(?) What were the reasons for this and the results in the initial years after they re-opened it.
		My memories are just of the opening day scenes (combat fishing) on the news.
		I could be wrong, but it seems like I remember reading somewhere about the closing of the Lower Provo in the late 80's due to the drought then and low flows.
	www.utahonthefly.com /chat/showthread.php?t=6346 (349 words)

	refresh memory ??!?!! - LinuxQuestions.org
		If memory is marked as free then another program can still use it if it needs it, but if the same program is loaded again then some data is still in memory and can be used again so the program loads faster.
		Why would you bother to actively remove data in memory when it is no longer used...seems to me that would add overhead.
		If you mean that I didn't add buffers and cache to the free memory, I noticed that immediately and fixed it...if not, you will have to explain what you mean.
	www.linuxquestions.org /questions/showthread.php?threadid=368458 (1248 words)

	MicroMac 168-pin 5V EDO Memory DRAM DIMM
		The 168-pin 64-bit 5V EDO DIMM is the most commonly used memory module for the second generation Power Macintosh models.
		Typically they are installed individually, although in some selected Mac models they may be installed in pairs to allow interleaving to achieve an overall faster memory access.
		With today's powerful system software and the newest generation application programs you need more memory, lots of it in fact, to run your computer efficiently.
	www.micromac.com /products/memory_dimm_168pin.html (592 words)

	Refresh Your Memory - Trubble's CatBox
		It was suggested to me to refresh my memory when I am feeling guilty for leaving.
		I plan on writing more as it comes to memory, and have my daughter starting a journal every night, I let her lay in bed and stay up 15 minutes later than normal, just to write.
		Anyway, as far as memories go, I thought I remembered it all, too.
	www.drirene.com /catbox/index.php?showtopic=4655 (1546 words)

	Memory
		Consolidation hypothesis of short-term memory into long-term memory through rehearsal.
		Supported by accidents causing retrograde amnesia (inability to retrieve past memories).
		Assumes physiologically different processes for short- and long-term memory (short-term memory can be easily disrupted).
	homepage.psy.utexas.edu /homepage/Class/Psy301/Delville/Classes/October27Memory/Index.html (259 words)

	Memory Refresh Error - ABXZone.com Forums
		My new P4C800 deluxe (2x256 kingston kvr400x64C3/256 2.5V 3-4-4 Value RAM) was running fine for a few days but then it starting doing one beep during startup (Memory refresh error).
		I tried reseating RAM, removing each of them and retrying (they are both in the blue slots).
		Is this likely to be a memory problem or a memory controller problem ?
	www.abxzone.com /forums/showthread.php?t=52486 (141 words)

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