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Topic: Memory scrubbing

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	IBM Redbooks \| Active Memory
		Memory scrubbing is an automatic daily test of all the system memory that detects and reports memory errors that might be developing before they cause a server outage.
		Memory mirroring is roughly equivalent to RAID-1 in disk arrays, in that memory is divided in two ports and one port is mirrored to the other half.
		Memory mirroring must be disabled when using hot-add and due to the way memory is implemented in the x445, the port you are adding memory to must be empty before you add memory, and DIMMs must be added in multiples of two.
	publib-b.boulder.ibm.com /Redbooks.nsf/RedbookAbstracts/tips0259.html?Open (914 words)

	POWER2 Fixed-Point, Data Cache, and Storage Control Units -- Page 3
		Memory data is loaded one word per cache macro per cycle in a four-word memory system, and two words per cache macro per cycle in an eight-word system.
		Memory addresses are moved from the PBUS into the PBUS Memory Queue and then moved out to main memory via the memory row/column address generation logic.
		The scrub sequence consists of three memory transfers: a read operation to detect errors, a write operation to correct the errors, and a read operation to verify that the data has been corrected.
	www-03.ibm.com /servers/eserver/pseries/hardware/whitepapers/power/fxu_3.html (4040 words)

	Kingston Technology Company - Tools - Ultimate Memory Guide (Site not responding. Last check: 2007-11-03)
		Memory scrubbing is a feature initially implemented by most major server OEMs when ECC DIMMs first became available.
		Memory scrubbing refers to a process that actively reads memory during idle periods to search for and correct errors in memory.
		The speed of memory is limited by the speed of the memory bus, which is the slowest link in the process.
	www.kingston.com /tools/umg/umg05b.asp (3288 words)

	Compaq.com - ProLiant 800 - Question and Answer (Site not responding. Last check: 2007-11-03)
		The existing EDO memory works in an asynchronous manner to the system clock having to wait for a request before transmitting data where the new SDRAM memory works in a synchronous manner being able to send information on the next available clock cycle instead of having to wait for a request from the chipset controller.
		The form of "memory scrubbing" that HP provides is only the most basic level of fixing memory errors as they are detected by the server, as an adjunct to ECC protection.
		The memory scrubbing function of the most recent crop of HP servers occurs as an extension of the ECC protection offered in the memory controller that is part of the chipset.
	h18000.www1.hp.com /products/servers/proliant800/questionandanswer.html (1902 words)

	Bi-STAR(tm) Technology
		Scrubbing, ECC, and repair are performed on-chip, without using system resources; the Bi-STAR™ functions do not interfere with normal memory access, and are completely transparent to the rest of the system.
		Redundant memory areas are common to all memory chips, but remapping is usually performed in a coarse-grained manner, perhaps four rows or columns at a time.
		Memory devices without Bi-STAR™ ignore the random, recoverable bit-flips caused by radiation; if a bit is flipped, the error remains until a new value is written to that location.
	www.tezzaron.com /technology/Bi_STAR.htm (956 words)

	esp@cenet description view
		The memory controller in which the scrubbing mechanism is implemented comprises at least memory control logic for controlling the flow of data to and from memory in addition to a single data buffer, although in the preferred embodiment, separate read and write data buffers are provided.
		When ready, the memory control logic issues a memory scrub command to a datapath state machine, which controls the flow of data to and from memory, to signal that the corrected data within the read buffer is to be written back to the memory location from which it came.
		Subsequently, the MCL issues a memory scrub command to the DPSMs on the MEMCMD bus (via the ICIC) to signal that the corrected data within the read buffer is to be written back to the memory location from which it came.
	v3.espacenet.com /textdes?&DB=EPODOC&IDX=EP775343 (4388 words)

	Bulk Memory Device Driver
		This memory, usually still treated as a sequential access device, is mostly used to hold telemetry during periods when ground contact is precluded.
		Bulk memory is susceptible to errors on read and write, especially in the space environment, and needs multi-layer protection such as triple-modular redundancy (TMR), horizontal and vertical cyclic redundancy codes (CRC), error correcting codes (ECC), and scrubbing.
		With a memory management unit (MMU), even using 1:1 mapping of virtual to physical addresses, the MMU can be used to re-map around failed sections of memory.
	flightlinux.gsfc.nasa.gov /docs/Bulk_Memory_Device_Driver.html (2016 words)

	Methods and apparatus for high-speed mass storage access in a computer system - Patent 5987627
		The public memory includes staging registers which are used for conversion between the CPU local bus word size and the internal private memory word size as may be necessary, including pipelining as required.
		A mass storage apparatus according to claim 1 wherein the private memory is isolated from the CPU local bus in that the private memory is accessible to the CPU local bus only through the staging buffers and under control of the logic means.
		Data scrubbing is the generic name for a method of reading stored information and error correction codes, checking the information against the codes and repairing any detected errors found in the data.
	www.freepatentsonline.com /5987627.html (12327 words)

	Tips for using RAS features for storage systems
		Memory controllers typically implement ECC to protect against silent data corruption caused by events such as alpha particle hits or system-induced errors that compromise data integrity.
		A memory controller may also implement a hardware engine called a memory scrubber that can be scheduled to continually read and write to memory locations looking for soft and hard failures.
		The effect of these scrub writes do not cause any noticeable degradation to memory bandwidth, although they will cause a greater latency for that one very infrequent read that is delayed due to the scrub write cycle.
	www.computerworld.com /printthis/2005/0,4814,103821,00.html (940 words)

	Real World Technologies - Error Correcting Memory - Part I
		One method that has been deployed in the quest to ensure DRAM memory system reliability is the concept of memory scrubbing.
		Active memory scrubbing consumes power and bandwidth, since the error detecting and correction circuitry is currently contained in the DRAM controller, data would need to be transported to and from DRAM chips.
		Memory systems that operate in extreme environments or future memory systems with significantly higher error rates may deploy scrubbing as an active defense against uncorrectable multi-bit errors.
	www.realworldtech.com /page.cfm?ArticleID=RWT121603153445&p=10 (303 words)

	Compaq.com - Compaq ProLiant 800 - Question and Answer (Site not responding. Last check: 2007-11-03)
		The new SDRAM memory works in a synchronous manner being able to send information on the next available clock cycle instead of having to wait for a request from the chipset controller.
		Memory can be expanded to a maximum of 1 GB by installing four 256 MB 100MHz registered ECC SDRAM DIMMs (one in each DIMM socket).
		Apart from memory and processors, new features, such as support for up to 1 GB of RAM, support for 18 GB drives, and an integrated dual channel SCSI controller, differentiate the new ProLiant 800 models from their 6/350 predecessor.
	h18000.www1.hp.com /products/servers/proliant800/350e-400-450-qa.html (1876 words)

	Multiple bit computer memory errors happen on Gravity Probe B mission
		If that location is in an area of memory that is not currently being used, the MBE is said to be "benign." In fact, most of the MBEs we've seen thus far in the mission have occurred in benign memory locations.
		Once the engineer determines the correct value of a bad memory location in the spacecraft's computer, he creates a set of commands that are manually sent to the spacecraft during a telemetry pass to patch the bad location with the correct value.
		Because the CPU is executing instructions while EDAC memory scrubbing is in process, it is possible for the CPU to access a memory location that was, say, struck by a stray proton from the sun near the SAA region of the Earth, before the EDAC system detected the error.
	www.spacew.com /forum/index.php/topic,250.0.html (1506 words)

	memscrub.c (Site not responding. Last check: 2007-11-03)
		26 / 27 28 #pragma ident "@(#)memscrub.c 1.18 06/02/11 SMI" 29 30 / 31 * i86pc Memory Scrubbing 32 * 33 * On detection of a correctable memory ECC error, the i86pc hardware 34 * returns the corrected data to the requester and may re-write it 35 * to memory (DRAM or NVRAM).
		Machines which do not re-write this to 36 * memory should add an NMI handler to correct and rewrite.
		This scrubber 46 * guarantees that all of physical memory is accessed periodically 47 * (memscrub_period_sec -- 12 hours).
	cvs.opensolaris.org /source/xref/on/usr/src/uts/i86pc/os/memscrub.c (1056 words)

	Guild Companies - The Enterprise Windows & Linux Advisor
		This chipset supported up to 16 GB of main memory in a single server and four memory banks that were interleaved to generate 4.1 GB/sec of memory bandwidth.
		Main memory is interleaved four ways, which means customers have to add memory four sticks at a time (so that 512 MB of base memory is actually four 128-MB sticks of 200 MHz DDR SDRAM).
		Memory is expandable from the base 128 MB to the maximum 4 GB.
	www.itjungle.com /mid/mid022002-story04.html (738 words)

	32 GBits Mass Memory Board (under Development) (Site not responding. Last check: 2007-11-03)
		The memory board is made up of 2 memory banks of 80 x 256Mbit SDRAMs.The board provides individual power switching for each of the two banks.
		To correct automatically the SDRAM errors induced by radiation, memory scrubbing and SDRAM refreshing are done locally in each Memory Board in a transparent way for the user.
		The design of the Memory Board is based on the experience of ASTRIUM over the past 30 years in space equipment production, withstanding severe space environments such as cosmic radiation and thermal vacuum.This memory board was developed for an export program.
	www.astrium.eads.net /corp/prod/00000881.htm (282 words)

	POWER2 Fixed-Point, Data Cache, and Storage Control Units
		Memory bus bandwidth is augmented by a store-back D-cache design with two change bits per line.
		As memory data arrives, it is written into the D-cache in the second half of the cycle.
		Load-through data is bypassed from the memory data latch and sent to the FXU or FPU in the first data cycle of all loads.
	www.rz.uni-karlsruhe.de /rz/docs/MPI/Workshop.mhpcc/ibmhwsw/fxu.html (7617 words)

	Ace's Hardware - General Message Board
		Scrubbing can correct a whole cacheline that could be wrong
		By itself, scrubbing is an atomic (performed without interruption), transparent (done in background independent of the rest of the system) engine that does add another layer of robustness and reliability.
		Memory RAS is a very ineresting topic, and I'm happy to make use of my knowledge in the subject.
	www.aceshardware.com /forums/read_post.jsp?id=105050731&forumid=1 (322 words)

	FlightLinux Project
		Although we usually think of bulk memory as a secondary storage device with sequential access, it may be implemented as random access memory within the computer's address space.
		The memory scrubbing technique is derived from the current scheme used by SSTL, as is the paging scheme.
		The bulk memory device driver, which uses the 32-megabyte modules of extended memory as a file system, will be added next.
	flightlinux.gsfc.nasa.gov /docs/FlightLinux_LL.htm (7540 words)

	Real World Technologies - A Preview of Intel's Bensley Platform (Part I)
		A 3.2GHz point-to-point uni-directional serial interconnect is routed between the memory controller and the buffers.
		CRC is used to detect errors in address or commands from the memory controller.
		Memory scrubbing and logging are also implemented, but that is hardly news; Lindenhurst also supported scrubbing to detect single bit errors before they can become uncorrectable double bit errors.
	www.realworldtech.com /page.cfm?ArticleID=RWT110805135916&p=4 (722 words)

	Intel® Server System SR870BH2 - Tested Memory [PDF]
		The memory control Subsystem in the 870 chip set supports memory scrubbing, single-bit error correction and multiple-bit error detection and the Intel® Single Device Data Correction feature.
		Functionality issues may occur if mixed memory types are installed in the same server system. Intel recommends that memory modules of identical size, type, banking and stacking technology, and vendor are installed in each server system.
		Customers who choose to use mixed memory module configurations assume responsibility for ensuring that these configurations are compatible and tested.
	support.intel.com /support/motherboards/server/sr870bh2/sb/cs-009506.htm (242 words)

	Intel® Server Board SE7501HG2 - Tested Memory List Report [PDF]
		The memory controller in the Intel® E7501 Chipset supports memory scrubbing, single bit error correction and multiple-bit error detection and the Intel® Single Device Data Correction feature.
		The Intel® Single Device Data Correction architecture gives the memory sub-system the ability to withstand a multibit failure within a DRAM device, including a failure that causes incorrect data on all data bits of the device.
		Intel recommends that memory modules of identical size, type, banking and stacking technology, and vendor are installed in each server system.
	support.intel.com /support/motherboards/server/se7501hg2/sb/CS-007343.htm (255 words)

	MPC Support
		The memory controller supports memory scrubbing, single-bit error correction andmultiple-bit error detection and Intel x4 SDDC support with x4 DIMMs.
		Therefore the maximum main memory configuration is 4 x 2 GB or 8 GB.
		Memory Information Note 1: Certain combinations of DIMM types in the same system can violate the write Ringback measurement specification during analog validation.
	support.mpccorp.com /apps/specs.asp?ID=7643 (847 words)

	P-9 - Solid-State Recorders - Space Applications - SEAKR Engineering Incorporated (Site not responding. Last check: 2007-11-03)
		The memory may be partitioned into numerous dynamically sized data segments.
		The memory array autonomously detects and maps out any memory faults encountered during the mission.
		Proprietary Error Detection and Correction (EDAC) And memory scrubbing algorithms are available for mission critical data recorder applications.
	www.seakr.com /home/space-applications/solid-state-recorders/p-9.html (350 words)

	Term Of The Day: November 7, 2005 (Site not responding. Last check: 2007-11-03)
		Memory scrubbing refers to the process of eliminating extraneous data from memory left over after an application has closed.
		Memory scrubbing can help prevent malicious users from obtaining usernames, passwords and other important personal information.
		With regard to ECC (Error Correction Code) memory (usually found in servers), this term refers to the periodic search for memory errors and the subsequent fixing of those errors.
	www.firstglimpsemag.com /Editorial/daily/dailyContent.asp?guid=&did=1001963 (85 words)

	Guild Companies - The Enterprise Windows & Linux Advisor
		Big Blue started hinting that MXT, which allows servers to have a virtual memory that is double the physical capacity of the memory chips in those servers, might come to market in late 2001 or early 2002, in an announcement the two companies made in June 2000.
		The MXT memory compression has been implemented in a ServerWorks chipset called MXT SystemI/O. The first Intel-based server that the MXT chipset will be used in is a modified xSeries 330 server appropriately called the xSeries 330MXT.
		In theory, the MXT memory compression can be used to either cut the number of memory sticks needed to reach a certain capacity in half, or to double the maximum memory capacity of a server that might only have two or four memory slots.
	www.itjungle.com /mid/mid022002-story03.html (1014 words)

	RedOrbit NEWS \| Dataram Introduces Memory Upgrades For IBM (Site not responding. Last check: 2007-11-03)
		All capacities support IBM's Chipkill technology, redundant spare memory chips with bit steering, memory scrubbing and thresholding to enhance data retention and overall system reliability.
		Dataram's focus on memory provides its customers with substantial savings of up to 50% or more when compared to the system vendor's memory.
		All Dataram memory products for IBM systems are guaranteed to be 100% compatible with IBM's hardware and software, and are backed by a lifetime warranty and free technical support.
	www.redorbit.com /modules/news/tools.php?tool=print&id=8853 (291 words)

	C H A P T E R 7 - Dynamic Reconfiguration on Sun Fire High-End Systems
		Description: When a domain is configured with a large amount of memory (340 Gbytes or more), either at boot time or due to subsequent DR operations, the memory scrubbing thread monopolizes a particular system lock for 60 to 90 minutes once every 12 hours.
		Any DR operation that attempts to configure or unconfigure memory in the domain during one of these windows hangs until the system lock is released.
		Description: If non-permanent memory is unconfigured, the system removes retired pages from the retired pages list to prevent them from becoming dangling pages - that is, pages that point to physical memory that would have been unconfigured.
	www.sun.com /products-n-solutions/hardware/docs/html/817-4190-11/starcat.html (988 words)

	Intel® E7520 Chipset For Embedded Computing - Overview
		DDR2-400 memory technology is ideal for storage and memory-intensive applications, providing up to 20% increase in memory bandwidth, and up to 40% decrease in power consumption over DDR 333.
		The memory subsystem interface to the MCH is dual channel, supporting three or four registered DIMMs per channel, depending on memory technology, for a total system bandwidth of up to 6.4 GB/second.
		In an x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC), provides error detection and correction for 1 to 4 data bits within a single device and provides error detection for up to 8 data bits within two devices.
	www.intel.com /design/chipsets/embedded/e7520.htm (513 words)

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