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	Metastability
		Metastability is the ability of a non-equilibrium state to persist for a long period of time.
		Usually metastability is due to a relatively slow phase transformation.
		For example at room temperature diamonds are metastable because the phase transformation to the stable graphite form is extremely slow.
	www.ebroadcast.com.au /lookup/encyclopedia/me/Metastable.html (114 words)

	Metastability in electronics - Wikipedia, the free encyclopedia
		Metastability in electronics is the ability of a non-equilibrium electronic state to persist for a long (and theoretically unboundable) period of time (see asynchronous circuit).
		Metastability is a distinct issue, different from this electrical noise issue, although they are sometimes confused, as they both involve flip flops loading erroneous values.
		Metastability remains poorly understood in some circles, and various engineers have proposed their own "pet circuits" said to "solve" or "filter out" the metastability.
	en.wikipedia.org /wiki/Metastability_in_electronics (754 words)

	Chip Design Magazine
		Metastability is a statistical event in which the output of a signal is not defined for an unpredictable amount of time.
		Metastability requires designers to add synchronizers to reduce the probability of metastable signals being sampled across clock domains.
		During netlist analysis, CDC coverage monitors and metastability effects injectors are generated for use in subsequent steps of the methodology.
	www.chipdesignmag.com /print.php?articleId=363?issueId=0 (1941 words)

	What Is Metastability?
		Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'.
		When a flip-flop is in metastable state, its output oscillate between '0' and '1' as shown in the figure below (here the flip-flop output settles down to '0').
		In the simplest case, designers can tolerate metastability by making sure the clock period is long enough to allow for the resolution of quasi-stable states and for the delay of whatever logic may be in the path to the next flip-flop.
	www.asic-world.com /tidbits/metastablity.html (881 words)

	FPGA-FAQ 0017 Tell me about Metastability
		The most common approach to minimizing the problems of metastability propagating into our synchronous systems is to use a synchronizing circuit to take the asynchronous input signal, and align it to the timing regimen of the rest of the system.
		The best way to deal with the metastable problem (the synchronization of an asynchronous signal feeding into and affecting a synchronous system) is to synchronize the signal with a multi stage synchronizer, comprizing of no more than 2 or more flipflops, connected as a shift register, and clocked by the clock of the destination domain.
		Unfortunately, the duration of the metastable state in the first latch is unbounded, and so there is no guarantee that it will be resolved by the time the second latch is opened.
	www.fpga-faq.org /FAQ_Pages/0017_Tell_me_about_metastables.htm (4860 words)

	EDN -- 06.23.94 Keep metastability from killing your digital design
		To find the probability of a synchronizer failure due to metastability, set t' equal to the maximum time that a synchronizer flip-flop can be metastable without affecting a succeeding flip-flop.
		Therefore, t' is usually the time interval between the active clock edge at the first flip-flop and the next active clock edge at the succeeding flip-flop, minus the setup time of the second flip-flop and minus the path delay between the two flip-flops (Fig 3).
		The path of the potentially metastable output is assumed to be entirely inside one PLD, from one flip-flop through the feedback to another flip-flop, both clocked by the same clock.
	www.edn.com /archives/1994/062394/13df2.htm (2542 words)

	VMEbus Asynchronous Bus / Metastability
		Metastability arises in any flip flop when its setup time is violated.
		When a flip flop experiences metastability, unintended effects can occur in downstream circuitry unless proper design techniques are used.
		Since flip flops are employed to indicate the state of an event, it is important that the period of indeterminacy not affect downstream circuitry.
	www.vita.com /vme-faq/metastability.html (842 words)

	TechXclusives - Metastability Delay and Mean Time Between Failure in Virtex-II Pro FFs (Site not responding. Last check: 2007-11-05)
		If the metastable flip-flop drives two destinations with different path delays, one destination might clock in the final data state, while the other clocks in the intermediate metastable state.
		If a metastable event in the first flip-flop increases the settling time on QA so much that QC misses the change, but QB still captures it on the next rising clock edge, this error can be detected by feeding the XOR of QB and QC into a falling-edge triggered flip-flop.
		By changing the clock frequency, and thus the clock half-period, the amount of acceptable metastable delay on the QA output can be varied, and the resulting frequency of metastable events may be observed on the counter outputs.
	www.xilinx.com /xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_metastability&iLanguageID=1&iCountryID=1 (1324 words)

	Metastability effects simulation for a circuit description patent invention (Site not responding. Last check: 2007-11-05)
		The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing.
		The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
		In contrast, metastability effects are known to arise in physical implementations of circuit 100, due to the difference in the two clock signals on paths 105 and 106.
	www.freshpatents.com /Metastability-effects-simulation-for-a-circuit-description-dt20051201ptan20050268265.php (2797 words)

	photovoltaics.html (Site not responding. Last check: 2007-11-05)
		Metastability of anion vacancies in II-VI and chalcopyrite semiconductors
		It is concluded that the sometimes observed small beneficial effects of light-soaking relies only on a feeble balance between the detrimental effect of recombination centers and the beneficial effect of increased space charge density which occurs when the complexes change persistently their charge state upon illumination.
		It is suggested that metastability in a CIGS solar cell indicates a less-than-ideal state, and that efforts should be undertaken to produce solar cells not showing metastability.
	www.sst.nrel.gov /topics/pv.html (1298 words)

	Chaos, metastability, and Buridan's donkey.
		The purpose of this brief page is to put the Buridan's donkey paradox of metastability into the context of the theory of dynamical systems which exhibit deterministic chaos, and to make a link with the Zeno paradox which is also concerned with the calculus, limit points, and the representation of numbers.
		As with the simple mechanical problem of balancing a pencil on its point, it is found that the time taken to leave the unstable fixed point depends on how close the system is set (in the absence of noise) to the fixed point in the first place.
		However, the problem with metastability is that one does not know, a-priori, how long to wait before assuming that the output has settled.
	www.ee.surrey.ac.uk /Personal/D.Jefferies/donkey.html (720 words)

	DesignWare Technical Bulletin
		The probability of a single random transition on the D input of a synchronizing flip-flop to cause metastability is proportional to the amount of time it takes for q_int to pass through the "twilight zone" between stable states divided by the period of the synchronizing clock.
		Even though this probability is, in most cases, very low for a single event, the probability of metastability over a specific period of time is multiplied by the number of asynchronous transitions seen on the D input during this period of time.
		In the simplest case, designers can tolerate metastability by making sure the clock period is long enough to allow for the resolution of quasi-stable states as well as whatever logic may be in the path to the next flip-flop.
	www.synopsys.com /news/pubs/dwtb/q398/frame_dwtb4.html (755 words)

	Michael Ward - Dynamic metastability for reaction-diffusion equations
		For instance, this metastability occurs in the propagation of thin interfaces for phase separation models, including the Cahn-Hilliard equation, which has applications to material science.
		The speaker will illustrate metastable behavior for certain classes of partial differential equations of reaction-diffusion type and will show how asymptotic, spectral and numerical analysis can be used to obtain a precise characterization of the slow dynamics.
		A necessary condition for metastability in these diverse types of reaction-diffusion equations is that the spectrum associated with the linearization of the partial differential equation around a certain robust canonical solution, such as a standing wave, contains exponentially small eigenvalues.
	camel.math.ca /Events/winter97/w97-abs/node2.html (206 words)

	Large Deviations and Metastability - Cambridge University Press (Site not responding. Last check: 2007-11-05)
		Metastability is first described on physical grounds, following which more rigorous approaches to its description are developed.
		Metastability I: general description, the Curie-Weiss model and contact processes; 5.
		Metastability II: the models of Freidlin and Wentzell; 6.
	www.cambridge.org /uk/catalogue/catalogue.asp?isbn=0521591635 (283 words)

	Metastability and Synchronous Design
		This is a general concept that helps the designer ensure that problems of metastability are designed out of circuits.
		The net effect of these asynchronous inputs is that for the devices in our system that are receiving these signals, we can’t guarantee that we will satisfy the setup and hold times, so metastability becomes inevitable.
		As shown in the Lattice application note this is using a flip-flop for each asynchronous input that we recognize may become metastable.
	www.uwm.edu /Course/318-457/meta/meta.htm (459 words)

	Metastability of Superheated Colloidal Crystals
		Metastable crystals' structure and dynamics, in particular, reveal long-ranged attractions consistent in range and magnitude to the measured wall-induced attraction [
		It should not be viewed as evidence for pairwise attractions, however, since the direct interaction measurements described in Section 2 largely rule out this interpretation.
		In this sense, observations on metastable superheated colloidal crystals serve as a bridge between pair interaction measurements and measurements of bulk phase behavior.
	www.physics.nyu.edu /~dg86/granadab/node4.html (527 words)

	Re: metastability (Site not responding. Last check: 2007-11-05)
		The difference between a stable and a metastable state is the same as between a global and a local minimum.
		A metastable state describes a local minimum in the energy of a system (usually a thermodynamic system).
		Under controlled circumstances, the metastable state may persist even though it is not globally energetically favorable.
	www.lns.cornell.edu /spr/2005-10/msg0071785.html (291 words)

	Metastability and Firmware
		Clearly at reasonable rates the odds of the two asynchronous signals arriving closely enough in time to cause a metastable situation are low; measureable, yes, important, certainly.
		The second flop’s output will be “correct” after two clocks, since the odds of two metastable events occurring back-to-back are almost nil.
		But “correct” means the second stage’s output will not be metastable: it’s not oscillating, nor is it at an illegal voltage level.
	www.ganssle.com /articles/MetastabilityandFirmware.htm (2093 words)

	Ian G. Clark - Metastability Bibliography
		Data on the metastability characteristics of the flip-flop are gathered and analyzed.
		The device is held close to metastability by a feedback loop, and is therefore relatively insensitive to circuit asymmetries and drift.
		The metastability window, resolution time and time interval between the clock edge and the time t/sub meta/ are evaluated as functions of power supply and the type of body-connection topology.
	iangclark.net /metastability.html (5561 words)

	University of Notre Dame/Interdisciplinary Center for the Study of Biocomplexity/Center News
		One approach to accelerating biomolecular simulations is to simulate explicitly only certain slow degrees of freedom of interest, incorporating the effects of the remaining ``fast'' variables through effective stochastic models.
		Metastability is a prevalent feature in biomolecular systems.
		We show in particular how the metastability can lead to various effective stochastic equations for the slow degrees of freedom depending on the relations between the physical parameters and properties of the potential energy landscape.
	www.nd.edu /~icsb/kramer_abstract.htm (139 words)

	Metastability and Firmware
		Metastability occurs only when clock and data arrive almost simultaneously; the odds increase as clock rates soar.
		At reasonable rates, the odds of the two asynchronous signals arriving closely enough in time to cause a metastable situation are low.
		Hardware designers smugly cure their metastability problem using the two stage flops described previously.
	www.embedded.com /shared/printableArticle.jhtml?articleID=9900237 (2029 words)

	Inducing Metastability (Site not responding. Last check: 2007-11-05)
		The metastable window on a flip-flop is extremely narrow, perhaps only a few picoseconds wide.
		Once you set the potentiometer to create a lot of metastable events, drift in the flip-flop's metastable window will soon cause the circuit to fall off the metastable cusp, and the circuit will return to normal operation.
		Noise present within the circuit prevents me from setting the data-clock skew accurately enough to produce repeatable metastable delays much larger than about 5x the normal clk-Q interval, however, it does permit me to observe plenty of those very rare events using a digital scope with infinite- persistence.
	www.sigcon.com /Pubs/news/4_4.htm (802 words)

	Metastability in Flip-Flops
		Villela writes: In your book you talk about metastability in flip- flops, and you suggest that two flip-flops are a good way to avoid it.
		The essence of metastability is this: when the data input violates the setup and hold window, if it transitions close enough to the exact sampling moment within that window, the flip-flop may take LONGER than the normal clk-Q delay to make up its mind.
		As the flip-flop is deciding what to do it may stay LOW, and then later pop HIGH (or vice- versa), or it may jump one way, and then come back.
	www.sigcon.com /Pubs/news/3_15.htm (341 words)

	Metastability (Site not responding. Last check: 2007-11-05)
		Novotny and Rikvold, with postdoc Ramos and graduate students, continue their studies of the dynamics of metastable states near first-order phase transitions.
		The constrained-transfer-matrix method for calculating nucleation rates, previously introduced by Rikvold, will continue to be used whenever feasible to study the models for ferromagnetic materials [2].
		In particular we propose to use this method to investigate metastability in the anisotropic square-lattice Ising model, as well as to compare the constrained-transfer-matrix study of a quasi-one-dimensional Ising model [3] with Monte Carlo simulations and droplet calculations of the same model.
	www.csit.fsu.edu /research/matsci/metastable.html (615 words)

	Digital Logic MetaStability and Flip Flop MTBF Calculation
		The combination of the two values determine the width of the Metastability window.
		In most cases newer logic families have smaller Metastability windows which reduce the chance of the device going Metastable.
		Output waveforms due to signal timing Da, Db, Dc 'Da' produces a normal output, as the data does not violate the Set-up or Hold time of the device [in relation to the clock].
	www.interfacebus.com /Design_MetaStable.html (1009 words)

	( ESNUG 225 Item 3 ) ---------------------------------------------- [8/24/95] (Site not responding. Last check: 2007-11-05)
		Since this is a problem that all digital designers face at sometime, I decided to write up a brief refresher on metastability calculations including the answer to my previous question.
		If the input just happens to be changing at the critical time, the output may go metastable and take a little longer to resolve itself to a stable state.
		Experimentally, metastability is measured by clocking an evenly distributed random input into a flip-flop and measuring the time until the output has stabilized.
	www.deepchip.com /items/0225-03.html (805 words)

	Metastability and Nucleation
		However, in order to qualify as a challenge, a physical phenomenon should not only be important, it should also be difficult to study.
		The formation of a novel phase from the metastable parent phase proceeds through the formation of a “critical nucleus”.
		Clusters of the novel phase that are smaller than this critical size tend to disappear spontaneously - clusters that are larger than critical can continue to grow into a macroscopic domain of the novel phase.
	www.europhysicsnews.com /full/04/article4/article4.html (472 words)

	Embedded.com - Metastability and Firmware
		Slower logic (like 74HCxx) has a much wider metastable window than faster devices (say, 74FCTxx).
		With a 10MHz clock and 10kHz data rate, using typical but not terribly speedy logic, metastable errors occur about once a minute.
		Some designs will never have a metastability problem.
	www.embedded.com /story/OEG20010718S0067 (2385 words)

	SOCcentral: 0-In Introduces Automatic Verification of Metastability Effects (0-In Design Automation, Inc. 6432) (Site not responding. Last check: 2007-11-05)
		CDC-FX automatically synthesizes a metastability effect generator into a RTL description of a design.
		The generator introduces metastability effects by analyzing simulation and intelligently injecting signal errors whenever metastability may arise -- at every clock-domain crossing in the design, whether synchronized or not.
		The injected metastability errors stress the design during simulation of the original RTL description using existing testbenches and existing end-to-end checks which exposes functional and performance defects.
	www.soccentral.com /results.asp?entryID=6432 (488 words)

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