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	New Mexico Ornithological Society
		The NMOS Field Notes Database is now available for searching!
		The 45th Annual Meeting of the New Mexico Ornithological Society will be held Saturday, May 5, 2007, at Camp Washington Ranch and Retreat near Carlsbad in Eddy County.
		Sorry, we are experiencing technical difficulties with the database at the moment.
	www.nmosbirds.org (397 words)

	NMOS Database Overview
		The New Mexico Ornithological Society (NMOS) has partnered with the Natural Heritage New Mexico (NHNM) to develop a searchable database of the Society's publications containing field note observations of the Society's membership.
		The NMOS Field Notes have been compiled and entered into the database by NMOS volunteers and NHNM employees.
		For example, if you would like to know all of the species identified by a specific observer in one, two, or more counties, select these variables and the results of your query will be presented in a table which can be viewed and subsequently saved to your computer.
	nhnm.unm.edu /partners/NMOS (194 words)

	Semiconductor cmos devices and methods with nmos high-k dielectric formed prior to core pmos dielectric formation ...
		A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.
		NMOS devices within an I/O region having higher operation voltage requirements employ a high-k dielectric layer and a first oxide layer as dielectric layers.
		A second oxide layer is formed within NMOS regions of the core and I/O regions and a nitridation process is performed that nitrides the second oxide layer and the high-k dielectric layer.
	www.freshpatents.com /Semiconductor-cmos-devices-and-methods-with-nmos-high-k-dielectric-formed-prior-to-core-pmos-dielectric-formation-dt20061102ptan20060246716.php (1720 words)

	NMOS logic - Wikipedia, the free encyclopedia
		While nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with nMOSFETs), it has several shortcomings as well.
		The worst problem is that a DC current flows through an nMOS logic gate when the PDN is active, that is whenever the output is low.
		These disadvantages are why nMOS logic was supplanted by CMOS logic both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.
	en.wikipedia.org /wiki/NMOS_logic (411 words)

	NMOS
		The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the output and low-voltage rail, while a resistor is placed between the output and the high-voltage rail.
		While NMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can literally be made with one type of component), it has several shortcomings as well.
		These disadvantages are why NMOS logic has been supplanted by CMOS both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.
	www.ebroadcast.com.au /lookup/encyclopedia/nm/NMOS.html (285 words)

	NMOS: Negative-channel metal-oxide semiconductor (Site not responding. Last check: )
		Negative-channel metal-oxide semiconductor (NMOS) is a type of semiconductor that is negatively charged so that transistors are turned on or off by the movement of electrons.
		NMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits.
		NMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).
	www.javvin.com /hardware/NMOS.html (57 words)

	NMOS Image Sensors, Hamamatsu (Site not responding. Last check: )
		NMOS linear image sensors are self-scanning photodiode arrays with large active area, high UV sensitivity and high dynamic range.
		These devices are used to measure moderate to high light levels and have excellent resistance to deterioration caused by exposure to ultraviolet light.
		NMOS arrays are used in spectrometers, HPLC detectors and X-ray imagers.
	sales.hamamatsu.com /en/products/solid-state-division/image-sensors/nmos.php?GLBSESSID=85d0ed1378f0bb077c24559f05245865 (174 words)

	NMOS II
		The NMOS II team continued to attend ISSCC for several years, which was critically important given HP Loveland’s geographic isolation from Silicon Valley, the epicenter of chip development.
		In the early NMOS process, the wafer was prepared for diffusion by first growing a relatively thick layer of silicon dioxide, a field layer, over the entire chip.
		Another of the problems related to the shrinking dimensions of the NMOS II process was unwanted aluminum diffusion down through the relatively shallow (1.6 μm) doped source and drain regions in the FETs.
	www.hp9825.com /html/nmos_ii.html (2875 words)

	Object-Oriented Principles and MWFM NMOS (Site not responding. Last check: )
		AOCs are based on the concepts of object classes and object modelling, but the object classes in the hierarchy are active, which means that upon instantiation of an object to a class the properties, behavior and management policies contained in the relevant AOC are automatically applied to the object without configuration by the user.
		The AOCs are fundamental to the operation of MWFM NMOS and Cisco Mobile Wireless Fault Mediator, so it is important to have an understanding of their content.
		MWFM NMOS is made of eight components which interact to enable all devices on a network to be discovered and an accurate network topology model developed.
	www.cisco.com /univercd/cc/td/doc/product/rtrmgmt/cw2k4mw/mwfm/mwfm20/mwfmeng/ob.htm (1958 words)

	Strained Silicon and Transistor Performance - Technology & Research at Intel (Site not responding. Last check: )
		In NMOS devices (N for negative) the signal carriers, or electrons, have a negative charge.
		Current is on when a NMOS transistor gate is at high voltage, and off when its gate is at low voltage.
		The current in a PMOS transistor flows opposite to that of an NMOS transistor.
	www.intel.com /technology/silicon/si12031.htm (923 words)

	Monolithic Integration of Carbon Nanotube Devices with Silicon MOS Technology
		The catalyst island is located on the source (S) of an NMOS transistor (identified by the overlaid device symbol).
		When a supply voltage Vdd equal to the NMOS gate voltage is applied, it drops by about one transistor threshold voltage after the first transistor in the chain.
		Implemented in the NMOS technology, it is the first instance of monolithic integration of CNT with MOS technology.
	pubs.acs.org /cgi-bin/sample.cgi/nalefd/2004/4/i01/html/nl0349707.html (2382 words)

	SignalExpress - NMOS Characterization Using DAQmx and DMM - Example - Development Library - National Instruments
		The source and body are both grounded and the device will operate, or in other words, a drain current will be induced based on voltages applied at the gate and drain of the transistor.
		The positive terminal of ao0 of the DAQmx device should be connected to the gate terminal of the NMOS transistor, and the negative terminal (ground) should be connected to the source terminal of the transistor.
		The positive terminal of ao2 of the DAQmx device should be connected to the low terminal of the DMM measuring the drain current, and the negative terminal (ground) should be connected to the source terminal of the transistor.
	sine.ni.com /apps/we/niepd_web_display.display_epd4?p_guid=F6FDF2F74C904497E0340003BA7CCD71&p_node=201141&p_source=external (320 words)

	NMOS Tutorial Example (Site not responding. Last check: )
		The nmos structure shown in the following figure will be used to for this tutorial.
		When the pointer moves to a position so that the rubber-band rectangle is approximately of 110U x 8U in size, release the left button and a solid ivory colored filled rectangle appears on the canvas.
		This rectangle represents the part of the cross-section of the substrate on which the nmos transistor will be built and hence represents the starting building block.
	www.eecs.umich.edu /mistic/help/nmos_tut.html (1443 words)

	Dynamic CMOS Paper
		Since the NMOS devices in the ON state forms a pull-down path to GND and the PMOS device is always ON, there will be times during circuit operation where a path is formed from VDD to GND.
		Due to the finite pull down time of the NMOS logic block, during the very first portion of the evaluation phase, the output will always register an output high state for at least a brief moment in time before the output charge can be removed via the pull-down path to GND.
		Note that care must also be taken to insure that the input logic signals to the NMOS logic block are correct and stable for the complete duration of the evaluation stage or a similar logic error could occur.
	www.lauraknauth.com /academic/DynCMOS.html (3778 words)

	NMOS Transistor Characterization with the NI PXI-4071 7 1/2-digit FlexDMM- Developer Zone - National Instruments
		A field-effect transistor (FET) is a device whose ability to carry current is varied by an applied electronic field; thus, a FET is a voltage controlled device.
		NMOS transistors consist of three terminals: gate, drain, source, and body.
		NMOS transistor characterization is one example that demonstrates National Instruments capabilities with low current applications.
	zone.ni.com /devzone/cda/tut/p/id/3736 (1072 words)

	Electrical isolation in integrated circuits - Patent 5422507
		The integrated circuit device of claim 3, wherein each nMOS transistor is disposed in a p-well that is the body of the transistor and which is doped sufficiently such that a body-to-source back bias of -0.5 volts causes a field threshold increase of approximately 2 volts or greater, for a field oxide thickness of 2000.ANG..
		The integrated circuit device of claim 9, wherein the body of the nMOS transistor including a p-well is doped sufficiently that a body-to-source back bias of -1.0 volts causes a field threshold increase of approximately 4 volts or greater, for a field oxide thickness of 2000.ANG..
		4, the body connections of all the nMOS transistors (N1, N2 and N3) advantageously are connected to the ground reference voltage and the body connections of all of the pMOS transistors (P1, P2 and P3) are connected to Vdd.
	www.freepatentsonline.com /5422507.html (4592 words)

	Ram/Research
		During the precharge phase, the clock input is low, turning off the NMOS device and switching on the PMOS device, this pulls the output high, as there is no path from the output to the ground.
		A dynamic gate replaces the slow PMOS transistor of static CMOS gate is replaced by a clocked PMOS transistor, which does not load the input as in the case of the static gate.
		The width of the PMOS transistors used in the design is 6µm and that of NMOS transistor is 3µm.248 PMOS transistors and 248 NMOS transistors were required to build an 8-bit static Brent-Kung adder.
	www.iit.edu /~kottven/research.htm (2086 words)

	Object-oriented Principles and MWFM NMOS (Site not responding. Last check: )
		The AOCs are fundamental to the operation of Fault Mediator NMOS and Cisco MWC Fault Mediator, so it is important to have an understanding of their content.
		Fault Mediator NMOS is made of eight components which interact to enable all devices on a network to be discovered and an accurate network topology model developed.
		To enable Fault Mediator NMOS components to communicate with third-party applications such as help desk or trouble ticketing systems, or even other Fault Mediator NMOS domains, DIST can use a series of configurable listeners to filter information to the particular application.
	www.cisco.com /univercd/cc/td/doc/product/rtrmgmt/cw2k4mw/mwfm/mwfm31/fmref31/object.htm (1993 words)

	Auner, Siy, & Naik
		NMOS Inverter with Resistive Load--Introduces the simplest gain stage consisting of one NMOS transistor with resistive load.
		NMOS Inverter with NMOS load - Introduces another simple gain stage using two NMOS transistors.
		NMOS Inverter with PMOS Current Load - Introduces a simple gain stage using NMOS transistor with PMOS current load.
	www.ineer.org /Events/ICEE1997/Proceedings/paper332.htm (1908 words)

	NE Asia Online2005 Mar : Strained Si Enters Practical Use with Both nMOS, pMOS (Site not responding. Last check: )
		Strained Si technology requires that pMOS and nMOS channels are strained in different directions to improve the performance of both, and the resulting process complexity led most companies to only use the technology on one of the two types.
		This approach has been frequently used in the past, especially to generate strain on the nMOS side, but the Si film growth parameters were tweaked to make it possible to apply the required compressive strain on the pMOS side as well.
		Evaluation results were nMOS transistor drive performance at 1050µA/um for an off current of 70nA/um, superior to IBM's results of 940µA/um for an off current of 100nA/um.
	neasia.nikkeibp.com /neasia/000509 (575 words)

	from nmos to cmos
		NMOS process is not compatible to CMOS process.
		Nmos device and CMOS device is different implematation of a design.
		In term of circuit design there is a different of the design when you are design in NMOS or CMOS.
	www.edaboard.com /ftopic66633.html (168 words)

	APPENDIX G TRANSISTORS AND THE IMPLEMENTATION OF LOGIC (Site not responding. Last check: )
		The NMOS and PMOS transistor are used in the CMOS family of integrated circuits.
		For the NMOS when the gate is LO the transistor is cut off (switch open) and when the gate is HI the transistor is saturated (switch closed).
		Remember that for NMOS gate HI means switch closed and gate LO switch open and for PMOS gate HI means switch open and gate LO switch open.
	www.thiel.edu /digitalelectronics/chapters/appg_html/appg.htm (1309 words)

	WBG Integrated Circuit Development at Purdue (Site not responding. Last check: )
		The circuit technology is enhancement-load NMOS, with the load transistor operated in the non-saturating mode with a separate V
		This circuit is a master-slave D-type flip-flop with the Q-bar output fed back to the D input to form a binary counter.
		Right Side: SiC NMOS half adder circuit, truth table, and operating waveforms at 304 °C. As the A and B inputs change, note that the Sum and Carry outputs obey the binary rules in the truth table.
	www.ecn.purdue.edu /WBG/Device_Research/NMOS_ICs/Index.html (267 words)

	New Mexico Ornithological Society
		The NMOS now offers two $1000 research grants each year to help support research on
		A short research proposal (2 pages maximum) must be submitted describing the nature of the project and how the allocated funds are to be spent (e.g., on gas, tape recording, specific equipment, etc.).
		Grant awards will be announced at the NMOS Annual Meeting on 5 May 2007.
	www.nmosbirds.org /grants.html (159 words)

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