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School of Computer & Information Science - University of South Australia |
 | | Like the Nx586, AMD K5, and Intel's "Pentium Pro", the the third stage of the 10-stage 68060 pipeline translates the 680x0 instructions to a decoded RISC-like form (stored in a 16 entry buffer in stage four), and uses resource renaming (with fourty rename registers) to reorder instructions. |
 | | It seems interesting to note that in the case of the NS320xx and Z-80000, non mainstream processors gained many advanced design features well ahead of the more mainstream processors, which presumably had more development resources available. |
 | | One possible reason for this is the greater importance of compatibility in processors used for computers and workstations, which limits the freedom of the designers. |
| www.cis.unisa.edu.au /~cisbkg/cso/resources/cpu_history.html (16732 words) |