Non-Uniform Memory Access

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Topic: Non-Uniform Memory Access

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	Cache Coherent Non Uniform Memory Access (ccNUMA) Support
		Access from a processor to node local memory is fast, as is the case with small SMP systems.
		Access to memory in other nodes is slower.
		The use of fine-grained interleaving, in which the memory is interleaved across the nodes at a small granularity, is mutually exclusive with respect to ccNUMA optimizations.
	msdn.microsoft.com /library/en-us/appendix/hh/appendix/enhancements5_0dd92ce5-8ca1-4956-b7ad-8d8272239a93.xml.asp (1131 words)

	An Overview of MPP Systems
		Non Uniform Memory Access systems are those systems in which memory access times are not uniform, but rather dependent on the route to and latency at the node containing the requested memory line.
		Memory associated to processors in such a way is called local memory from the viewpoint of that processor because it has direct access to that node's memory ports and need not go through any memory network routing.
		In the NUMA architecture, the memory was distributed among the various processor nodes and memory accesses to the local memory would happen faster than accesses that had to go to memory stored on a remote processor node.
	www.blight.com /~ja-wells/311/report.html (4210 words)

	brecht.txt
		While these previous studies investigate the importance of scheduling techniques for reducing the number of non-local memory accesses by co- locating processes with the data being accessed, our work investigates the importance of scheduling techniques for reducing the cost of required non-local memory accesses in environments where processes and data cannot be co-located.
		Increasing Memory Latencies The NUMAness of a system can be thought of as the degree to which memory access latencies are affected by the distance between the requesting processor and the desired memory location.
		This results in systems with a number of levels in the memory hierarchy and memory access latencies that vary with the number of levels of the hierarchy that must be traversed.
	www.usenix.org /publications/library/proceedings/sedms4/full_papers/brecht.txt (6682 words)

	numa_intro(3)
		NUMA, or Non-Uniform Memory Access, refers to a hardware architectural feature in modern multi-processor platforms that attempts to address the increasing disparity between requirements for processor speed and bandwidth and the bandwidth capabilities of memory systems, including the interconnect between processors and memory.
		NUMA Enhancements to Basic UNIX Algorithms and Default Behaviors For NUMA, modifications to basic UNIX algorithms (scheduling, memory allocation, and so forth) and to default behaviors maximize local accesses transparently to applications.
		Topology-aware placement of data The operating system attempts to allocate memory for application (and kernel) data on the RAD closest to where the data will be accessed; or, for data that is globally accessed, the operating system may allocate memory across the available RADs.
	www.helsinki.fi /atk/unix/dec_manuals/DOC_51/HTML/MAN/MAN3/0488____.HTM (803 words)

	IBM Redbooks Introduction to NUMA on xSeries Servers
		But by limiting the number of processors that directly access that memory, performance is improved because of the much shorter queue of requests.
		Every CPU can also access the memory of any other CPU in the system but at longer latency.
		NUMA effectively means that every processor or every group of processors has a certain amount of memory local to it.
	www.redbooks.ibm.com /abstracts/tips0476.html (1078 words)

	Glossary Search Results
		NUMA (Non-Uniform Memory Access) - A multiprocessing architecture where each processor or small group of processors has its own group of memory chips.
		NUMA typically scales better than SMP architectures, where memory is all accessed at the same speed in one large bank.
		Accessing memory local to the processor is faster than accessing remote memory on other processor boards.
	www.geek.com /glossary/glossary_search.cgi?n (3216 words)

	NUMA: Non-Uniform Memory Access
		The physically distributed memory of Origin systems implies that access times are no longer uniform, it varies depending on the distance from the memory being accessed.
		Initial latencies for remote memory accesses are the largest, the added latency for each additional router the data must pass through after the first are negligible.
		The hypercube configuration implies that in the worst case memory access grows as the logarithm of the number of processors.
	www.arc.unm.edu /~bbaltz/SGI/ohw_mod/ohw_Slide_22.html (143 words)

	36514.000622&ELEMENT_SET=DECL
		Such computer systems are said to have a non- uniform memory access because each processor has lower access latency with respect to data stored in the system memory at its local node than with respect to data stored in the system memory at a remote node.
		NUMA systems can be further classified as either non-coherent or cache coherent, depending upon whether or not data coherency is maintained between caches in different nodes.
		The complexity of cache coherent NUMA (CC-NUMA) systems is attributable in large measure to the additional communication required for hardware to maintain data coherency not only between the various levels of cache memory and system memory within each node but also between cache and system memories in different nodes.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=00/36514.000622&ELEMENT_SET=DECL (5731 words)

	6.6. Non-Uniform Memory Access (NUMA) Machines
		When memory is allocated by the parent, it is distributed among all the nodes in a round-robin fashon using a stride of MAXLMD.
		When the FMS Memory Management routines are called to allocate memory by a child thread, the memory is automatically placed on the node where the child thread is executing.
		One design goal of a NUMA machine is to make the routers as fast as possible to minimize the difference between local and remote memory references.
	www.fmslib.com /fmsman/doc/numa.html (990 words)

	NUMA Frequently Asked Questions
		NUMA is one way of reducing the number of CPUs competing for access to a shared memory bus.
		NUMA alleviates these bottlenecks by limiting the number of CPUs on any one memory bus, and connecting the various nodes by means of a high speed interconnect.
		That said, local memory is typically defined to be the memory that is on the same node as the CPU currently running the process.
	lse.sourceforge.net /numa/faq (1248 words)

	Linux Scalability Effort: NUMA Group Homepage
		On NUMA systems, optimal performance is obtained by locating processes as close to the memory they access as possible.
		NUMA awareness within the scheduler is necessary in order to support locality of processes to memory - primarily by dispatching a process on the same node through the duration of the procesess' life.
		For optimal performance, the kernel needs to be aware of where memory is located, and keep memory used as close as possible to the user of the memory.
	lse.sourceforge.net /numa (440 words)

	Print Version - Alternate Architectures for Data Warehousing Business intelligence, data warehousing and analytics editorial from DMReview
		A processor in one building block can access the memory in another building block, but not as quickly as it can the memory that is local.
		The exceptional difference between the two is that memory in all of the building blocks is seen as one global memory area.
		In addition, a single global memory limits the processing to what can be supported by the memory subsystem.
	www.dmreview.com /editorial/dmreview/print_action.cfm?articleId=907 (1039 words)

	Parallel Hardware Architecture
		In uniform disk access systems, or shared disk systems, as shown in Figure 2-2, the cost of disk access is the same for all nodes.
		In NUMA configurations, the cost of accessing a specific location in main memory is different for some of the CPUs relative to others.
		Memory - The component used for programmatic execution and the buffering of data.
	www.usd.edu /oracle/doc/paraserv.817/a76968/pshwarch.htm (1272 words)

	NUMA - Computerworld
		Processors also can access memory pools on each of the other nodes, though the time taken for that access varies with how far the nodes are from one another.
		Currently, a typical NUMA configuration ranges from eight to 16 processors, supports up to 32G bytes of memory, has more than 1T byte of disk space and runs Unix.
		NUMA reduces some of the bus congestion of SMP by having the processors in a node communicate with one another and their local memories via separate, smaller buses.
	www.computerworld.com /printthis/1998/0,4814,43424,00.html (580 words)

	Memory access - Tech Tips - Memory Access Violations
		Memory access violations can be caused by many different things.
		Random Access Memory or RAM is a type of (An electronic memory device) In today's computers memory access is becoming very slow when compared to
		We study the effect of memory access ordering policies on processor performance.
	cutesky.com /c/memory-access.html (216 words)

	ITworld.com - LINUX TIPS AND TRICKS - NUMA
		Non-uniform memory access (NUMA)is a relatively new method of configuring a cluster of processors in a multiprocessor system so that they share memory locally.
		NUMA adds an intermediate level of memory shared among a few processors so that most data accesses don't have to travel on the main bus.
		Put differently, NUMA introduces an additional cache layer that reduces the number of accesses to the external memory.
	www.itworld.com /nl/lnx_tip/10192001 (571 words)

	Helix Systems Overview
		All of the SGI systems use a ccNUMA architecture (cache coherent, non-uniform memory access) to combine the scalability of distributed memory machines with the ease of use of traditional shared memory SMP computers.
		Helix is a shared memory SMP (symmetrical multiprocessor) computer, meaning that each of its processors has direct access to all of system memory.
		Nimbus is a shared memory multiprocessor SGI 3400 supercomputer that is used for applications requiring large computational or memory resources.
	helix.nih.gov /systems (507 words)

	Request for Comments
		This idea is basically what NUMA (Non Uniform Memory Access) architectures address.
		There have been several "shared memory" on top of clusters packages written, but the are not a universally useful solution.
		In practice, it is very difficult to do this and get the performance you need without resorting to special hardware and software.
	www.beowulf.org /pipermail/test/2000-January/000175.html (319 words)

	InterSystems Caché - Caché Technology - Technical Documents - Caché Technology Directions - 2002
		NUMA, which stands for Non-Uniform Memory Access, addresses this issue by dividing key hardware elements, such as processors and memory, into "building blocks".
		A number of hardware vendors (including HP, IBM and Sun) have introduced large-scale computer systems that employ Non-Uniform Memory Access (NUMA) architectures.
		While all CPUs can access all memory, local access (within a building block) is much faster than foreign access to pages in other building blocks.
	www.intersystems.com /cache/technology/directions/numa.html (427 words)

	NUMA - TheBestLinks.com - Non-Uniform Memory Access, Disambig, National Underwater and Marine Agency, ...
		NUMA, Non-Uniform Memory Access, Disambig, National Underwater and Marine...
		NUMA - TheBestLinks.com - Non-Uniform Memory Access, Disambig, National Underwater and Marine Agency,...
		This is a disambiguation page, i.e., a navigational aid which lists other pages that might otherwise share the same title.
	www.thebestlinks.com /NUMA.html (112 words)

	Memory Placement on the Origin2000
		Since the Origin2000 is a NUMA (Non-Uniform Memory Access) system, the time it takes for a CPU to access a memory location varies according to the location of the memory relative to the CPU.
		Remote memory accesses are slower than local memory accesses and hence the user will pay a penalty.
		For serial applications with memory requirements that will fit on the node on which it runs, this is not an issue.
	www.ncsa.uiuc.edu /UserInfo/Consulting/Tips/Memory_Placement.html (1040 words)

	NUMA - Enterprise Networking Planet - Practical Advice for Managing Your LANs, WANs, SANs and WLANs
		It's called non-uniform because the memory access times are faster when a processor accesses its own memory than when it borrows memory from another processor.
		Short for Non-Uniform Memory Access, a type of parallel processing architecture in which each processor has its own local memory but can also access memory owned by other processors.
		NUMA computers offer the scalability of MPP and the programming ease of SMP.
	networking.webopedia.com /TERM/N/NUMA.html (110 words)

	Uniformity of shared memory access
		: non-uniform memory access - typically exhibited by DSM architecture, memory locations incur different access delays depending on which processor accesses them.
		: uniform memory access - all processors have equal access time to any given memory location.
		: the memory consists only of the collective cache contents of the processors and data migrates to the requesting processor.
	www.cs.mu.oz.au /677/notes/node18.html (70 words)

	AppDev: Something You Should Know by Irena Kennedy
		NUMA is a computer memory design used in multiprocessors, where the memory access time depends on the memory location relative to a processor.
		The optimizer will avoid generating access plans using a hash join if it detects that a low memory situation may occur during query execution.
		NUMA can improve the performance over a single shared memory by a factor of roughly the number of processors (or separate memory banks).
	blogs.msdn.com /irenak/default.aspx (2402 words)

	4csc5551.doc
		A computer in which some locations in shared memory takes no longer to access that others are called as Non-Uniform Memory Access (NUMA).
		Shared memory multiprocessors and message-passing multiprocessors are the two types of multiprocessors.
		OpenMP is an execution to a sequential programming language to support shared memory MIMD computation.
	ouray.cudenver.edu /~kvrengan/4csc5551.doc (521 words)

	A primer on NUMA (Non-Uniform Memory Access)
		Each processor uses the local memory for data and instruction sharing purpose and some of its internal computations are done in the internal local memory which leads to reduced memory contention resulting into higher program efficiency.
		"NUMA is a memory architecture used in multiprocessors wherein apart from the common system memory each processor has its own local memory which can be used for the processor's own computations.
	rootprompt.org /article.php3?article=6443 (112 words)

	Preparing for high-end Windows CNET News.com
		The Redmond, Wash.-based software company is working on support for a technology called non-uniform memory access, or NUMA, one method for designing large servers crammed with processors, said Sean McGrane, program manager for Microsoft's top-end Datacenter server.
		NUMA is named for the fact that it can take different amounts of time to fetch information from memory.
		When NUMA is running, Windows divvies up processing tasks to try to keep things running as fast as possible, McGrane said.
	news.com.com /2100-1001-884391.html (780 words)

	ccNUMA machines
		The most important ways to let the SMP nodes share their memory are S-COMA Simple Cache-Only Memory Architecture) and ccNUMA, which stands for Cache Coherent Non-Uniform Memory Access.
		On the other hand, because the memory is physically distributed, it cannot be guaranteed that a data access operation always will be satisfied within the same time.
		Another way is the directory memory, a special part of memory which enables to keep track of the all copies of variables and of their validness.
	www.phys.uu.nl /~steen/web01/ccNUMA.html (529 words)

	22C:116, Lecture 25, Spring 2002
		Non-Uniform Memory Access in a shared memory multiprocessor implies that all memory is shared, but each CPU has fast access only part of memory, its own local memory, and slower access to other parts of memory, the local memory areas of other CPUs.
		So long as the memory addresses likely to be used by the process are in the cache, it will run at full speed, but when the cache holds none of the process's memory addresses, the process will run very slowly until the cache is loaded.
		Modern cache designs allow memory words belonging to multiple processes to reside simultaneously in the cache, so on a uniprocessor, there is a reasonable chance that when a high priority processes is scheduled, it will find that many of the memory references it makes result in cache hits.
	www.cs.uiowa.edu /~jones/opsys/spring02/notes/25.html (622 words)

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