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Topic: OpenRISC


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In the News (Wed 24 Jul 19)

  
  OpenRISC - Wikipedia, the free encyclopedia
OpenRISC is an open source hardware RISC CPU design by OpenCores released under the GNU Lesser General Public License.
The design is implemented in the verilog hardware description language and has been manufactured successfully as an ASIC as well as being hosted in FPGA environments.
The GNU toolchain has been ported to OpenRISC to support development in several languages and Linux and uClinux have been ported to the processor.
en.wikipedia.org /wiki/OpenRISC   (101 words)

  
 Organization Heralds Open Source For Chips - Technology News by TechWeb
Nevertheless, the OpenCores organization said it is working on an OpenRISC version that executes the MIPS-I instruction set of MIPS Technologies, Mountain View, Calif., an ARM rival.
OpenRISC 1000, which is not a clone and executes its own set of instructions, is due to be available from the OpenCores website in a matter of days.
Lampret is still refining OpenRISC and has a superscalar version of the core, he also has a "lite" version which could be adapted to run MIPS-I code, Lampret said.
techweb.com /wire/story/TWB20000228S0009   (639 words)

  
 UC OpenRISC Project   (Site not responding. Last check: 2007-10-21)
UC OpenRISC Team was created due to a project developed in University of Cantabria including the design of a complete RISC microprocessor.
However, the OpenCores team working in the OpenRISC had already made that port, and because of this such work didn't seem to be necessary.
But there was no Real Time Operating System available for OpenRISC 1000 at that time, and work was started on a port of RedHat eCos in order to have all the tools necessary to sucessfully develop applications for the new microprocessor.
www.teisa.unican.es /~csanchez/index.html   (426 words)

  
 OpenRISC 1000   (Site not responding. Last check: 2007-10-21)
OpenRISC 1000 is an architecture of a family of open source, synthesizeable RISC microprocessor cores.
OpenRISC 1000 architecture is a predecessor of more powerful and feature richful next generation OpenRISC architectures.
Implementions of the OpenRISC 1000 architecture will be available in full source at this web site and will be supported with GNU software development tools, with a port of open source Linux operating system, with a port of open source Cygnus eCos real time operating system and with a architectural and implementation simulators.
linuxdevices.com /links/LK3998276224.html   (583 words)

  
 EETimes.com - Free 32-bit processor core hits the Net
An OpenRISC prototyping board comprises a Xilinx FPGA and Xilinx programmable-logic device.
Lampret is still refining OpenRISC and has a superscalar version of the core, dubbed OpenRISC 1002, that's optimized for speed.
He further claims to have a 'lite' version, the OpenRISC 1001, optimized for gate count that runs at 80 MHz in a Xilinx Virtex XCV50 and that provides 80 Mips of performance.
www.eetimes.com /story/OEG20000228S0007   (1779 words)

  
 Free 32-bit processor core hits the Net   (Site not responding. Last check: 2007-10-21)
Nevertheless, the OpenCores organization said it is working on an OpenRISC version that executes the MIPS-I instruction set of MIPS Technologies Inc. (Mountain View, Calif.), an ARM rival.
OpenRISC 1000, which is not a clone and executes its own set of instructions, is due to be available from the OpenCores Web site in a matter of days.
Lampret is still refining OpenRISC and has a superscala r version of the core, dubbed OpenRISC 1002, that's optimized for speed.
www.us.design-reuse.com /news/?id=1832&print=yes   (1726 words)

  
 OpenRISC is an open source open source RISC RISC CPU...
OpenRISC is an open source open source RISC RISC CPU...
"OpenRISC" is an open source open source RISC RISC CPU CPU design by OpenCores OpenCores released under the GNU Lesser General Public License GNU Lesser General Public License.
The GNU toolchain GNU toolchain has been ported to OpenRISC to support development in several languages.
www.biodatabase.de /OpenRISC   (96 words)

  
 Debugging with GDB: OpenRISC 1000
JTAG remote server can be either an or1ksim or JTAG server, connected via parallel port to the board.
OpenRISC 1000 Architectural Simulator, proprietary commands can be executed.
It is very similar to GDB trace, except it does not interfere with normal program execution and is thus much faster.
computing.ee.ethz.ch /sepp/gdb-6.0-mo/gdb_175.html   (164 words)

  
 EETimes.com - European Space Agency launches free Sparc-like core
Though the core has yet to be fully tested in hardware, its VHDL source code has been downloaded at least 150 times since Feb. 17 when the debugged core went up on the agency's Web site.
A spokeswoman for ARM Ltd., a leading licensor of processor cores, downplayed the impact of the free cores on her company's business.
OpenRISC 1000 was announced last week by an organization called OpenCores.
www.eetimes.com /story/OEG20000306S0096   (1364 words)

  
 Info Node: (gdb.info)OpenRISC 1000   (Site not responding. Last check: 2007-10-21)
OpenRISC 1000 ------------- See OR1k Architecture document (`www.opencores.org') for more information about platform and commands.
Example: `target jtag jtag://localhost:9999' `or1ksim COMMAND' If connected to `or1ksim' OpenRISC 1000 Architectural Simulator, proprietary commands can be executed.
Some implementations of OpenRISC 1000 Architecture also have hardware trace.
www.cs.vassar.edu /cgi-bin/info.cgi?(gdb)OpenRISC+1000   (340 words)

  
 Welcome to the UW ASIC Team
The OpenCores.org OpenRISC 1000 processor project involved a joint collaberation between the VLSI Team and the CMOS IC Team.
For information on the OpenRISC 1000 standard, please visit the OpenCores.org website: overview, architecture.
The role of the CMOS IC Team in the implementation of the OpenRISC 1000 processor was to design a 500 MHz PLL.
www.asic.uwaterloo.ca /project/openrisc.php   (75 words)

  
 Ace's Hardware
According to this EETimes article, an organization known as OpenCores has developed a freely available RISC CPU core known as the OpenRISC 1000.
This is somewhat similar to what Sun has done with SPARC, however, OpenRISC has very few, if any, legal strings attached.
Individuals could produce and sell entire systems based around OpenRISC (though the core is still very simplistic at this point in time).
www.aceshardware.com /read_news.jsp?id=338   (399 words)

  
 [No title]
Hmmm....it appears that the folks responsible for OpenRISC are defining a "common platform" environment for the OpenRISC processor.
Besides, OpenRISC must be good -- both ARM and MIPS have warned OpenCores to not produce a MIPS or ARM clone or risk serious legal complications.
There is one disadvantage to using the OpenRISC, though it is hardly a major issue: the basic unit of memory is now the 8-bit byte.
tunes.org /~nef/logs/forth/04.08.06   (3550 words)

  
 Gmane -- Mail To News And Back Again
The target is to port the linux >> > kernel on the openrisc CPU implemented.
This is of great >> > interest to run Linux on the openrisc.
>> > ===================== >> >> There is a lot of information available about this at the openrisc >> project page (http://www.opencores.com/projects/or1k/).
article.gmane.org /gmane.org.handasarabia.ofoq/32   (1376 words)

  
 News archive   (Site not responding. Last check: 2007-10-21)
It fixes two bugs found in previous snapshot, that caused problems in (1) some functions returning 64 bit values and (2) functions using lot of general purpose registers.
A snapshot of gcc OpenRISC version ported by UC OpenRISC Team is already avaible in download area.
Although it is a development version, it is completely usable and has been heavily tested by our team with satisfactory results.
bree.teisa.unican.es /~csanchez/oldnews.html   (276 words)

  
 openrisc, jp1 jtag debug utility
Posted: Tue Aug 30, 2005 8:15 am Post subject: openrisc, jp1 jtag debug utility
i've worked thru all of the openrisc HW and SW steps.
Posted: Tue Aug 30, 2005 4:16 pm Post subject: Re: openrisc, jp1 jtag debug utility
www.castalk.com /ftopic9494.html   (668 words)

  
 Electronic Equipment - software tool kits for openrisc
Electronic1 is a free, independent resource made available to you by a group of volunteer Electronic enthusists.
Now I am doing some programming on Openrisc processor on FPGA.
Xilinx tools set we can upload the makefile to it and run.
www.electronic1.net /detail-2796963.html   (77 words)

  
 Bug#298710: RFP: or1ksim -- OpenRISC 1000 architectural simulator
Bug#298710: RFP: or1ksim -- OpenRISC 1000 architectural simulator
Bug#298710: RFP: or1ksim -- OpenRISC 1000 architectural simu…
The aim of the OpenRISC project is to create a free, open source computing
people.debian.org /~terpstra/message/20050309.132629.e05919fb.en.html   (93 words)

  
 OpenRISC submission.   (Site not responding. Last check: 2007-10-21)
Let me introduce myself, i am one of developer wich contribute to opencores.org projects especialy working on porting toolchains for OpenRISC cpu.
OpenRISC is actualy a FPGA syntesiable completly opensource CPU wich is in the class of other porprietary leon, nios,ublaze,mips,arm cpus, with the exception that this one is really opensourced, and is used by crowd of entusiast but olso used by big companies in their silicon projects replacing proprietary mips/arm cores.
I want to ask maintainers on this list, basicaly what steps and what requirement need to folow to have OpenRISC suport in uclibc tree ?
busybox.net /lists/uclibc/2006-January/013883.html   (159 words)

  
 Electronic Equipment - Comparison of LEON2, Microblaze and Openrisc processors
Subject: Comparison of LEON2, Microblaze and Openrisc processors
Subject: Re: Comparison of LEON2, Microblaze and Openrisc processors
Whether it is open-source or not does not affect the performance...
www.electronic1.net /detail-9920337.html   (1355 words)

  
 Building OpenRISC tools for embedded development   (Site not responding. Last check: 2007-10-21)
This document is a step-by-step guide to installing all the OpenCores tools for cross development for an OpenRISC OR1000 system.
The tools are more appropriate for embedded development as opposed to Linux or ucLinux development.
Now logout and log back in again for these to take effect.
www.asisi.co.uk /or1k_embedded_0_1.html   (332 words)

  
 gEDA: Re: [openrisc] Verilog version of OpenRISC 1001   (Site not responding. Last check: 2007-10-21)
Subject: gEDA: Re: [openrisc] Verilog version of OpenRISC 1001
Hi Peter, what ever you do the code is still beta and I am currently modifying it to include current OR1K architecture changes.
If translator is freely available we can have automatically translated version of OR implementations (OR1003 which is bigger (MMU, caches) is underway) also in OpenCores CVS so that you don't have to track changes manually.
www.geda.seul.org /mailinglist/geda-dev29/msg00083.html   (163 words)

  
 Koders - openrisc-desc.h
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H #define CGEN_ARCH openrisc /* Given symbol S, return openrisc_cgen_.
*/ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) /* Enum declaration for openrisc hardware types.
www.koders.com /c/fidBC1C8A2715200EB534915107B0EC6AD72E6533DB.aspx   (882 words)

  
 Johan Rydberg - [PATCH] OpenRISC support for opcodes
Johan Rydberg - [PATCH] OpenRISC support for opcodes
From: Johan Rydberg
Here's a patch that add support for OpenRISC to opcodes.
www.cygwin.com /ml/binutils/2001-04/msg00291.html   (149 words)

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