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| | A DIGRESSION ON CHIPS (Site not responding. Last check: 2007-10-11) |
 | | Split an operation into several sub-operations, each executing in different sub-units of the chip in each clock cycle. |
 | | Each operation takes 4 clock cycles to complete, but operations are overlapped so that in cycle 2, operations B and A are both performed, in cycle 3, C, B, A are all performed, etc. Thus in 6 cycles, all three instructions are completed for all four stages. |
 | | This arithmetic pipeline operates in much the same way as instruction pipelining - namely, operations on different components of a long vector are overlapped. |
| www.math.buffalo.edu /~pitman/courses/cor501/HPC1/node5.html (388 words) |
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