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Topic: Orthogonal instruction set

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	Orthogonality - Wikipedia, the free encyclopedia
		are orthogonal with respect to Lebesgue measure on the interval from 0 to 2Ï.
		The Legendre polynomials are orthogonal with respect to the uniform distribution on the interval from â’1 to 1.
		The Laguerre polynomials are orthogonal with respect to the exponential distribution.
	en.wikipedia.org /wiki/Orthogonal (960 words)

	Orthogonal instruction set - Wikipedia, the free encyclopedia
		All computer architectures define the set of basic (fundamental) instructions that a computer conforming to that architecture must be capable of processing.
		As with a set of mathematical basis vectors, which must be orthogonal if they are to represent any vector uniquely, only an orthogonal instruction set can uniquely encode all combinations of opcodes, data types, registers, and addressing modes.
		Perhaps some of the bits that were used to express the fully-orthogonal instruction set could instead be used to express more virtual address bits or select from among more registers.
	en.wikipedia.org /wiki/Orthogonal_instruction_set (936 words)

	orthogonal - definition by dict.die.net
		N mutually orthogonal vectors span an N-dimensional vector space, meaning that, any vector in the space can be expressed as a linear combination of the vectors.
		For example, in logic, the set of operators "not" and "or" is described as orthogonal, but the set "nand", "or", and "not" is not (because any one of these can be expressed in terms of the others).
		Or, in logic, the set of operators `not' and `or' is orthogonal, but the set `nand', `or', and `not' is not (because any one of these can be expressed in terms of the others).
	dict.die.net /orthogonal (329 words)

	T3 VM Byte-code Instructions
		Most instructions have a fixed operand size, so the number of bytes of operand data can be deduced directly from the instruction's opcode; a few instructions, however, use varying-length operand data, in which case the size is encoded in the operand data.
		This instruction is the complement of the LJSR instruction, and is used to return from a local subroutine invoked with that instruction.
		Four separate instructions are provided so that calls to functions from up to four instruction sets can be efficiently coded; it is anticipated that most programs will rely on a small number of intrinsic function sets for their most common operations, so four such instructions will probably allow efficient instruction encoding for most programs.
	www.tads.org /t3spec/opcode.htm (13329 words)

	CmpSci 635 Lecture 5 (Site not responding. Last check: 2007-11-05)
		Orthogonal being the property that each operation on each data type is independent of the potential set of operand sources and destinations.
		The instruction set and the register set may go through several design iterations -- special registers may be needed to support certain operations such as setting operational modes, and these in turn may require changes to the fields in the register set.
		Instruction types are a particular source of decoding complexity, as the type field must first be decoded before the other fields, which slows the decoding slightly.
	www.cs.umass.edu /~weems/CmpSci635/635lecture5.html (1786 words)

	VM Spec The Structure of the Java Virtual Machine
		Instruction mnemonics shown above with trailing letters between angle brackets (for instance, iload_) denote families of instructions (with members iload_0, iload_1, iload_2, and iload_3 in the case of iload_).
		The widening numeric conversion instructions are i2l, i2f, i2d, l2f, l2d, and f2d.
		The narrowing numeric conversion instructions are i2b, i2c, i2s, l2i, f2i, f2l, d2i, d2l, and d2f.
	java.sun.com /docs/books/vmspec/2nd-edition/html/Overview.doc.html (9344 words)

	The Instruction Set
		In the instruction summaries that follow, the arguments an instruction pops from the stack or pushes onto the stack will be listed along with a brief description of their purpose and data type.
		Sets the auto flip Boolean in the graphics state to FALSE causing the MIRP[] and MIAP[] instructions to use the sign of control value table entries.
		Sets the instruction control state variable making it possible to turn on or off the execution of instructions and to regulate use of parameters set in the CVT program.
	developer.apple.com /fonts/TTRefMan/RM05/Chap5.html (8784 words)

	P8 CPU Documentation -- Instruction Set
		The instruction set of an educational CPU should be complete, and should illustrate the types of instructions normally supported by actual CPUs.
		An instruction with memory-indirect addressing specifies the memory address in which the address of the required data is stored.
		The indirect mode for this instruction set will be limited to register-indirect, and the register containing the address will always be the R Register.
	www.rexfisher.com /P8/P8_Instructions.htm (1598 words)

	INSTRUCTION SET ARCHITECTURE
		SPACE instructions are encoded in seven bits as an orthogonal combination of an opcode, a select mode and a flag update mode.
		Instructions can be divided by the CD bit into those that act on the control registers and those that act on the array.
		instruction allows both registers to be written with the same 36b value in one cycle.
	cag.lcs.mit.edu /~krste/space/space_vainn92/node2.html (1250 words)

	minimal instruction set
		Another way of counting the "size" of an instruction set is to count all possible distinct instructions (DI), all valid variations of "source register", "destination register", and "addressing mode".
		Once a cell is loaded into the instruction latch for execution, P is incremented, and then all of the instructions in that cell are executed, (possibly modifying P) from the first to the last.
		After all instructions in a cell have executed, the next cell of instructions is read from this new value of [P] into the instruction latch, P is incremented, and then all the instructions in that cell are always executed (possibly modifying P).
	www.rdrop.com /~cary/html/minimal_instruction_set.html (8453 words)

	Compilers and Architecture
		If there are 20 ways to implement an instruction sequence, it makes it difficult for the compiler writer to choose which is the most efficient.
		Instructions should be provided that bind the quantities known at compile time and not force run time bindings.
		Minimal instruction set with 32 GPRs, R0 is always 0.
	www.cs.umbc.edu /~plusquel/611/slides/chap2_3.html (413 words)

	About JFCL
		JFCL is the mnemonic for the DECsystem-10 instruction "Jump on Flag and CLear it." It’s as simple as that, but of course that’s only the beginning of the story, not the end.
		The entire —10 instruction set was summarized by a simple diagram that occupied just two panels of the pocket sized Quick Reference card.
		As a consequence, all the mnemonics in the instruction set had to have pronunciations so that they could be used in casual conversation.
	www.sonic.net /gizmos/Computers/JFCL.htm (1245 words)

	ZSP: FAQ (Site not responding. Last check: 2007-11-05)
		A: The ZSP DSP has a RISC-like instruction set that is orthogonal and there are very few mode bits for the compiler to have to work with.
		The instruction caches for all the cores are direct mapped; the first generation core data caches are fully associative.
		Both an instruction accurate and a cycle accurate simulator are provided.
	www.zsp.com /technology/zspfaq.html (1327 words)

	A Set of Standard Microprocessor Programming Cards
		In any event the layout of the card allows all the instructions to be scanned relatively quickly since the number of mnemonics is usually around 90 with one mnemonic per line.
		Processors with a powerful orthogonal instruction set such as the 68000 may at first sight seem less powerful than they really are when viewing the corresponding programming card.
		For some very simple microprocessors such as the 8021, the instruction set may be so simple as to allow the third page to be shortened.
	archive.comlab.ox.ac.uk /cards/cards.html (1990 words)

	The instruction set
		The instructions are stored in the registers themselves: the source and destination register numbers are coded as six bits each, and stored in the two halves of a sixteen bit value.
		Each instruction cycle involves reading the source register involved in the instruction and then writing to the destination register.
		For efficiency, the next instruction is prefetched while the destination register is being written, and hence there is one branch delay slot.
	www.quinapalus.com /wires10.html (261 words)

	Computer Architecture Encyclopedia Article, History, Biography @ Local Color Art (Site not responding. Last check: 2007-11-05)
		In the same way as a building architect sets the principles and goals of a building project as the basis for the draftsman's plans, so too, a computer architect sets out the computer architecture as a basis for the actual design specifications.
		Architecture is often defined as the set of machine attributes that a programmer should understand in order to successfully program the specific computer (i.e., being able to reason about what the program will do when executed).
		For example, part of the architecture are the instructions and the width of operands manipulated by them.
	encyclopedia.localcolorart.com /encyclopedia/Computer_architecture (1198 words)

	Orthogonal Instruction set.
		A quick search gave me this "orthogonal Instruction set means little overlapping of instruction functionality with other instructions." I read in one document which says "CISC architecture can result in an instruction set that is not orthogonal".
		Does that mean that many instructions in the I-set have same functionality i.e some instructions are redundant????
		If so why CISC architects need to code those redundant instructions, which otherwise would have saved many Gates on the chip and hence the power consumption.
	www.usenet.com /newsgroups/comp.dsp/msg03563.html (119 words)

	Comp.compilers: Re: Compiling to the Intel instruction set
		Re: Compiling to the Intel instruction set dido@imperium.ph (2004-06-09)
		Re: Compiling to the Intel instruction set samiam@moorecad.com (Scott Moore) (2004-06-25)
		Re: Compiling to the Intel instruction set freitag@alancoxonachip.com (Andi Kleen) (2004-06-30)
	compilers.iecc.com /comparch/article/04-06-125 (536 words)

	680x0 - internet resources (motorola 60k) (Site not responding. Last check: 2007-11-05)
		Although the ColdFire architecture is closely related to the 680x0, there are many simplifications to the instruction set.
		Nearly all of the differences are omissions from the 680x0 instruction set and addressing modes.
		This means that (with a few important exceptions detailed below), a 680x0 instruction which is implemented in ColdFire behaves in exactly the same way under the two architectures.
	www.eg3.com /WebID/embedded/680x0/blank/newsgroup/a-z.htm (287 words)

	orthogonal instruction set - FOLDOC Definition (Site not responding. Last check: 2007-11-05)
		An instruction set where all (or most) instructions have the same format and all registers and addressing modes can be used interchangeably - the choices of op code, register, and addressing mode are mutually indepentent (loosely speaking, the choices are " orthogonal ").
		This contrasts with some early Intel microprocessors where only certain registers could be used by certain instructions.
		If you have problems or comments con cerning our WWW service, please send e-mail to the following address: webmaster@NightFlight.com.
	www.nightflight.com /foldoc-bin/foldoc.cgi?orthogonal+instruction+set (87 words)

	orthogonal instruction set from FOLDOC (Site not responding. Last check: 2007-11-05)
		An instruction set where all (or most) instructions have the same format and all register can be used interchangeably - the choice of which register to use is orthogonal to the choice of instruction.
		This contrasts with some early Intel microprocessor s where only certain registers could be used by certain instructions.
		Previous : ORKID, ORM, orphaned i-node, orphan process, ORTHOCARTAN, orthogonal
	www.instantweb.com /foldoc/foldoc.cgi?orthogonal+instruction+set (83 words)

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