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Topic: PCI Configuration Space

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Peripheral Component Interconnect

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	PCI Configuration Space - Wikipedia, the free encyclopedia
		The first 64 bytes of configuration space are standardised; the remainder are available for vendor-defined purposes.
		The only standardised part of extended configuration space is the first 4 bytes at 0x100 which are the start of an extended capability list.
		Since on system boot, all PCI devices are in an inactive state, they do not have any addresses assigned to them by which the operating system or device drivers can communicate with them.
	en.wikipedia.org /wiki/PCI_Configuration_Space (605 words)

	Method and apparatus for intelligent configuration register access on a PCI to PCI bridge - Patent 6189063
		The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is closest to the CPU is the primary interface.
		The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is farthest from the CPU is the secondary interface.
		The bus that connects to a PCI to PCI bridge and is closest to the CPU is the primary bus and connects to the primary interface of the PCI to PCI bridge.
	www.freepatentsonline.com /6189063.html (4145 words)

	Peripheral Component Interconnect - Wikipedia, the free encyclopedia
		PCI 2.0, which was the first to establish standards for the connector and motherboard slot, was released on April 30, 1993.
		PCI was immediately put to use in high-end servers, replacing MCA and EISA as the server expansion bus of choice.
		PCI devices must have special hardware in order to support sharing an interrupt port as it needs a way to tell if an interrupt is for itself or for a separate device sharing the IO port.
	en.wikipedia.org /wiki/Peripheral_Component_Interconnect (644 words)

	Please title this page. (Page 5) (Site not responding. Last check: 2007-11-06)
		PCI is an open specification, all host systems that are compliant with the PCI specification are capable of hosting any PCI compliant peripheral device.
		The PCI local bus specification dictates how the interface the OS uses should be constructed in order to comply with the specific formats used for PCI configuration space.
		After PCI BIOS has initialized the hardware and devices on the PCI bus are all powered up, control of the bus is momentarily passed to the OS.
	www.ece.unh.edu /courses/ece707_4/pci.html (1462 words)

	Host-to-PCI address translation
		PCI I/O and PCI memory space may each be as large as four Gbytes.
		PCI I/O space uses a full byte address, so the EPIC combines the least significant bits of the system address with the packet size code to create the PCI byte address and the PCI byte enables.
		PCI memory space uses four byte-aligned addresses; smaller entities are addressed by bus byte enables.
	docs.hp.com /en/A3725-96022/ch07s03.html (549 words)

	PCI
		The Peripheral Component Interconnect (PCI) is a bus architecture that is generally cheaper and faster than some older bus architectures (see ``Bus'').
		Specifications for the PCI architecture are available from the PCI Special Interest Group.
		Drivers for PCI devices are expected to be able to share interrupts with other drivers for other PCI devices and should be coded appropriately.
	docsrv.sco.com /HDK_concepts/ddT_pci.html (574 words)

	Address Spaces & Transaction Routing (Site not responding. Last check: 2007-11-06)
		PCI Express supports the basic 256 byte PCI configuration space common to all compatible devices, including the Type 0 and Type 1 PCI configuration space header formats used by non-bridge and switch/bridge devices, respectively.
		As with PCI, registers associated with transaction routing are located in the first 64 bytes (16 DW) of configuration space (referred to in PCI Express as the PCI 2.3 compatible header area).
		The first of the configuration space registers related to routing are the Base Address Registers (BARs) These are marked “<1” in Figure 3-16 on page 137, and are implemented by all devices which require system memory, IO, or memory mapped IO (MMIO) addresses allocated to them as targets.
	www.informit.com /articles/article.asp?p=169100&seqNum=8 (2899 words)

	Manpage of lspci
		With older kernels, the PCI utilities have to use direct hardware access which is available only to root and it suffers from numerous race conditions and other problems.
		Also using -M on PCI access methods which don't directly touch the hardware has no sense since the results are (modulo bugs in lspci) identical to normal listing modes.
		The Linux PCI Utilities are maintained by Martin Mares .
	www.fifi.org /cgi-bin/man2html?lspci+8 (699 words)

	lspci (Site not responding. Last check: 2007-11-06)
		Avail- able only for root as several PCI devices crash when you try to read undefined portions of the config space (this behavior prob- ably doesnât violate the PCI standard, but itâs at least very stupid).
		The PCI utilities use PCILIB (a portable library providing platform- independent functions for PCI configuration space access) to talk to the PCI cards.
		The PCI Utilities are maintained by Martin Mares .
	gd.tuwien.ac.at /linuxcommand.org/man_pages/lspci8.html (666 words)

	Physics at Minnesota:
		The rationale behind the CPU I/O address map is as follows: (1) To provide 4 GB of dense space to completely map the 32-bit PCI memory space and (2) To provide abundant PCI sparse memory space since sparse-space has byte granularity and is the safest memory-space to use (for example, no prefetching).
		The main problem with sparse space is that it wastes CPU address space (for example, 16 GB of CPU address space maps to 512 MB of PCI sparse space).
		The system provides two PCI IO sparse-space regions: region A, which is 32 MB and is fixed in PCI segment 0-32 MB; and region B, which is also 32 MB, but is relocatable using the HAE_IO register.
	www.physics.umn.edu /support/manuals/digital/miata/Service/co_admap.htm?printer=yes& (961 words)

	[No title]
		In the jargon of the PCI specification, PCI bus 1 is described as being downstream of the PCI-PCI bridge and PCI bus 0 is up-stream of the bridge.
		All of these address spaces are also accessible by the CPU with the the PCI I/O and PCI Memory address spaces being used by the device drivers and the PCI Configuration space being used by the PCI initialization code within the Linux kernel.
		That PCI device is a child of the the PCI Bus's parent PCI bus.
	www.tldp.org /LDP/tlk/dd/pci.html (4364 words)

	LWN: Patch: Request for Comment on PCI Express Configuration Support design
		The PCI Express Specification also defines an "enhanced configuration access mechanism" which is essentially a Memory Mapped scheme to access this extended configuration region.
		To support access to the extended configuration region of the PCI Express devices (Although legacy CF8/CFC scheme will still work, but the configuration access space will be limited to 256 bytes only), we need to modify the PCI subsystem.
		At the time of PCI initialization/device enumeration the pci_root_ops and hence pci_dev->ops structure is set to pci_express_ops for PCI Express devices (identified by the existence of the PCI Express capability structure).
	lwn.net /Articles/30467 (503 words)

	Man Page: pci(4) (Site not responding. Last check: 2007-11-06)
		PCI devices are self-identifying - that is to say the PCI device provides configuration parameters to the system, which allows the system to identify the device and its driver.
		The configuration parameters are represented in the form of name-value pairs that can be retrieved using the DDI property interfaces.
		Driver configuration files can also be used to augment or override properties for a specific instance of a driver.
	www.cse.msu.edu /cgi-bin/man2html?pci?4?/usr/man (894 words)

	CAST PCI-M64 Core
		The main PCI-M64 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development.
		Implements 64 bytes of PCI Configuration Space registers; Configuration Space can be extended up to 256 bytes if required.
		Configuration Space Registers block implements the mandatory 64 bytes of PCI Configuration Space registers.
	www.cast-inc.com /cores/pci-m64/index.shtml (540 words)

	KDB kernel debugger and kdb command - PCI configuration space and I/O debugging subcommands
		The subcommands in this category are used to debug I/O errors and PCI configuration space errors.
		The dpcib (display PCI byte), dpcih (display PCI halfword), and dpciw (display PCI word) subcommands read data from the PCI Configuration Space.
		The mpcib (modify PCI byte), mpcih (modify PCI halfword), and mpciw (modify PCI word) subcommands write data to the PCI Configuration Space.
	publib16.boulder.ibm.com /pseries/en_US/aixprggd/kdb/kdb_pcicfgspaceiodebugsc.htm (899 words)

	Easily Porting MS-DOS Diagnostics to Linux LG #58
		PCI configuration space access isn't safe either because consecutive writes to the configuration address and data ports are required.
		PCI configuration space is accessed like I/O ports using a read and a write request (WORM_PCI_R, WORM_PCI_W).
		These functions are implemented in Wormhole using PCI BIOS calls defined in linux/pci.h.
	linuxgazette.net /issue58/taylor.html (1585 words)

	LinuxQuestions.org Man Pages Online
		With older kernels, the PCI utilities have to use direct hardware access which is available only to root and it suffers from numerous race con- ditions and other problems.
		Avail- able only for root as several PCI devices crash when you try to read undefined portions of the config space (this behaviour probably doesn't violate the PCI standard, but it's at least very stupid).
		SEE ALSO setpci(8) AUTHOR The Linux PCI Utilities are maintained by Martin Mares .
	man.linuxquestions.org /index.php?query=lspci&type=2&section=8 (779 words)

	How To Create a PCI Device Driver for Windows NT
		Since PCI is dynamically configurable, the operating system reserves the right to move the BARs as it sees fit.
		Find the PCI device with 3 FOR loops: one for the bus, one for the device number, and one for the function number.
		The interrupt value returned from the configuration space might look out of range when the driver is running on a checked build.
	support.microsoft.com /default.aspx?scid=kb;EN-US;Q152044 (1237 words)

	PCI Architecture
		The Interrupt Line field of the device's PCI Configuration header is used to pass an interrupt handle between the PCI initialisation code, the device's driver and the operating system's interrupt handling subsystem.
		These two address spaces are used by the devices to communicate with their device drivers running in the kernel on the CPU.
		PCI Bus 3 has another PCI-PCI bridge (Bridge 4) on it, it is assigned 3 as its primary bus number and 4 as its secondary bus number.
	clicker.sourceforge.net /docs/teacup/pcidoc/PCI-hardware-overview-draft.html (4225 words)

	YoLinux.com Hypertext Manpage Browser:
		With older kernels, the PCI util- ities have to use direct hardware access which is avail- able only to root and it suffers from numerous race condi- tions and other problems.
		Available only for root as several PCI devices crash when you try to read undefined por- tions of the config space (this behaviour probably doesn't violate the PCI standard, but it's at least very stupid).
		This is very useful for analy- sis of user-supplied bug reports, because you can display the hardware configuration in any way you want without disturbing the user with requests for more dumps.
	node1.yo-linux.com /cgi-bin/man2html?cgi_command=lspci (794 words)

	Re: Re: [XFree86] XFree86-4.4.0 Build On Solaris-8/SPARC [Configuration
		This is a dump of the PCI bridge's configuration space (i.e.
		This address space is divided into various sub-areas (system memory, PCI configuration, PCI I/O, PCI memory, to name a few).
		Its effect is to tell your PCI bridge to ignore most PCI errors that occur on its secondary bus segment.
	www.mail-archive.com /xfree86@xfree86.org/msg17650.html (661 words)

	NdisWritePciSlotInformation (Windows CE 3.0 Device Driver Developement) (Site not responding. Last check: 2007-11-06)
		This function writes a specified number of bytes to the PCI configuration space for an NIC on the PCI bus.
		Specifies the byte offset within the PCI configuration space at which to begin transferring the caller-supplied configuration information.
		Pointer to a caller-allocated buffer containing the PCI configuration information to be written.
	msdn.microsoft.com /library/en-us/wceddk/html/wceddkNdisWritePciSlotInformation.asp?frame=true (354 words)

	U.S. Pregrant 20040059843 - Dynamic PCI device identification redirection on a configuration space access conflict (Site not responding. Last check: 2007-11-06)
		A computer system reroutes a configuration cycle intended for an unused system bus address line to the IDSEL, or equivalent, configuration chip select input pin of a device which uses the same system bus address line as another device on the system bus.
		The programmable logic device detects PCI bus configuration cycles associated with a PCI bus AD line that is otherwise unused as a chip select during configuration cycles.
		The PCI device then effectively responds to the configuration read or write cycle as if its IDSEL input pin was hardwired to the switched AD line.
	cxp.paterra.com /uspregrant20040059843.html (258 words)

	lspci(8): all PCI devices - Linux man page
		Show hexadecimal dump of whole PCI configuration space.
		Use as PCI ID database instead of /usr/share/hwdata/pci.ids.
		Use Linux 2.1 style configuration access to directory instead of /proc/bus/pci.
	www.die.net /doc/linux/man/man8/lspci.8.html (697 words)

	Encyclopedia: PCI Configuration Space
		People who viewed "PCI Configuration Space" also viewed:
		32-bit PCI expansion slots on a motherboard 64-bit PCI expansion slots inside a Power Macintosh G4 The Peripheral Component Interconnect standard (in practice almost always shortened to PCI) specifies a computer bus for attaching peripheral devices to a computer motherboard.
		Plug and Play is a term used in the computer field to describe a computers ability to have new devices, normally peripherals, added to it without having to reconfigure or (ideally) restart the computer.
	www.nationmaster.com /encyclopedia/PCI-Configuration-Space (906 words)

	Re: Accessing MMIO PCI space - crossplatform (fwd)
		I/O regions are continous subsets of I/O spaces, which are the set of all addressable locations plus some operations defined to read and write these locations.
		The functions to do region management take (except for PCICFG space, see below) an 'struct _region' as an argument that has the following members: member description device (PCI) device this belongs to base_virt virtual base address base_io base address the device's address decoder responds to.
		In order to support PCI device autodetection, the pcicfg_find() function is provided.
	www.ggi-project.org /mailinglist/nov98/575.html (1428 words)

	kbAlertz: (178660) - Dumppci.exe is a sample Win32 application and kernel-mode drive that demonstrates how to ...
		Dumppci.exe is a sample Win32 application and kernel-mode drive that demonstrates how to dynamically load or unload a driver, scan all the PCI devices in the system, and display the PCI configuration space for each device.
		Currently, you can display the PCI configuration data in either a formatted ("-f" option) or raw ("-r" option) manner.
		For each PCI device, the driver retrieves the PCI configuration space information and places it in the Win32 application's buffer.
	www.kbalertz.com /kb_178660.aspx (629 words)

	PCIScope (Site not responding. Last check: 2007-11-06)
		PCIScope is a powerful, operating system independent, tool designed to explore, examine and debug PCI subsystems.
		Unlike other PCI tools, PCIScope bypass Windows and obtains all its information directly from the hardware: this feature makes PCIScope fully O/S independent enabling it to recognize devices ignored by Windows.
		With new PCI cards appearing daily, PCIScope gives developers the unique capability to add the new devices via simple text file.
	drivertools.net /Products/Utilities/EngineeringUtilities/PCIScope.htm (637 words)

	Access to PCI configuration space 0xcf8,0xcfc fails from linux command prompt - ReadList.com (Site not responding. Last check: 2007-11-06)
		Access to PCI configuration space 0xcf8,0xcfc fails from linux command prompt
		PCI configuration space (address 0xcf8 and 0xcfc registers).
		turn require access to the PCI configuration space registers.
	readlist.com /lists/redhat.com/redhat-list/0/1855.html (131 words)

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