
	Where results make sense

Topic: PLL

Related Topics

Frequency modulation

Linear predictive coding

Linear prediction

MUX

Optic nerve

Affection

Laaland

Typhoon

TLP

Taihape

Rick Santorum

Ice Palace

RC2

Brunswick

3LO

In the News (Tue 7 Jul 09)

Northern Trust

Marvin Harrison

Peter Chernin

Gary Locke

Match Play

Penelope Cruz

Mickey Rourke

AR Rahman

Danny Boyle

Hugh Jackman

	PLL & Clocking Glossary
		The lock output indicates that the PLL output clock is stable and in phase with the reference clock. The two requirements for a PLL to obtain lock are that the reference clock and feedback clock are frequency matched and phase aligned.
		Both the PLL internal and external clock outputs are phase shifted with respect to the PLL clock input.
		Therefore, the PLL phase aligns the input reference clock with the clock signal at the ports of the registers in the logic array or the input/output element (IOE).
	www.altera.com /support/devices/pll_clock/glossary/pll-glossary.html (1954 words)

	PLL modeling and verification in a cycle-simulation environment
		Inclusion of the PLL in the S/390 two-cycle simulation environment meant that a VHDL description had to be written to behave properly in a cycle-simulation environment, yet emulate the PLL with sufficient accuracy.
		The method chosen for emulating the PLL was to describe a function generator capable of producing the required output waveforms as a derivative of the multiply bits and another key variable, the cycles per reference clock period (CPR period).
		Prior to the advent of the PLL behavior, a scannable latch was implemented in the clock logic to permit the output to be altered by 180 degrees.
	www.research.ibm.com /journal/rd/435/vanhuben.html (5586 words)

	Phase-locked loop - Wikipedia, the free encyclopedia
		The variable oscillator component of the PLL may be implemented using a clock source (such as a crystal oscillator), two counters (one up/down), and a digital comparator.
		The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.
		Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated.
	en.wikipedia.org /wiki/PLL (3267 words)

	Pll circuit patent invention
		The PLL circuit of the present invention includes a voltage-controlled oscillator, a loop filter, and a charge pump which controls a voltage of the loop filter while the voltage-controlled oscillator is not oscillating.
		A voltage-controlled oscillator 501 of the PLL circuit shown in the figure oscillates at a particular frequency fo according to an voltage value input at an oscillation control voltage input terminal 502, to output an oscillating signal from a voltage-controlled oscillator output terminal 503.
		As shown in the figure, the PLL circuit disclosed in patent document 3, furthering the concepts of patent document 2, includes an automatic voltage control device 813 which records in an analog manner a voltage value of the loop filter 510 being applied while the PLL circuit is in operation.
	www.freshpatents.com /Pll-circuit-dt20060608ptan20060119440.php (2450 words)

	Performing Transient Analysis on PLL Frequency Synthesizers
		A PLL can be considered a subsystem within a larger communications system, so it is appropriate to analyze this type of network with the help of a system-level simulator.
		Since a PLL can be considered a subsystem within a larger communications system, it is appropriate to analyze this type of network with the help of a system-level simulator, such as the Symphony communication system designer within the Serenade software suite.
		A PLL is primarily a nonlinear device because its phase detector is nonlinear.
	www.ansoft.com /news/articles/PLL.cfm (2664 words)

	What is phase-locked loop? - a definition from Whatis.com - see also: PLL, phase-lock loop
		PLLs are frequently used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM).
		A PLL consists of a voltage-controlled oscillator (VCO) that is tuned using a special semiconductor diode called a varactor.
		Since a PLL requires a certain amount of time to lock on the frequency of an incoming signal, the intelligence on the signal (voice, video, or data) can be obtained directly from the waveform of the measured error voltage, which will reflect exactly the modulated information on the signal.
	searchnetworking.techtarget.com /sDefinition/0,,sid7_gci783790,00.html (432 words)

	Pll architecture patent invention
		A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.
		The output of the VCO 14 is taken as the output of the PLL and is also fed back to a feedback divider 16 that divides the frequency of the VCO output.
		The smaller the division factor N in the feedback divider, the finer the resolution of the PLL output frequency.
	www.freshpatents.com /Pll-architecture-dt20051215ptan20050275473.php (1207 words)

	PLL Policy: Changing at the Speed of Velocity Management
		Under the old PLL policy, according to DA Pamphlet 710-2-1 dated 28 Feb 94 in Supply Update 14, units were authorized to stock PLL "to support a unit’s daily organizational maintenance operations." This was for a prescribed number of days of supply based on the average customer wait time (ACWT).
		In light of these problems, PLL continues to undergo rapid changes in policy to determine the most cost effective and efficient way to ensure that PLL parts are available when, where and in the proper amounts needed.
		PLL stockage for demand-supported items is based on prescribed number of days of supply based on the average customer wait time (ACWT), now 10 days.
	www.quartermaster.army.mil /oqmg/Professional_Bulletin/1997/Spring/pll.html (1736 words)

	Diagnostic Ultrasound: PLL and ALL Fibrosis
		The PLL runs along the posterior surface of the vertebral bodies, narrowing over the middle of the bone and expanding over the ends of the bodies and discs where it is anchored firmly and, like its anterior counterpart (ALL), it acts as a powerful stabilizer of the intervertebral joint.
		The utilization of intervertebral joint and longitudinal scanning allows the PLL and ALL tissues to be within the view of the sonogram, since it is not obscured by bony or other hard tissues.
		The sonographic presence of a posterior curve associated with the central PLL (Types 2-4) inflammation may be considered suggestive, although not diagnostic, of tension to the PLL as a result of a recent disc bulge.
	www.chiroweb.com /archives/15/03/22.html (1441 words)

	PLL
		The classical digital pll consists of four main blocks: a phase frequency detector (pfd), a loop filter, a voltage controlled oscillator (vco), and an optional counter in the feedback path.
		For example, if the pll is to output a 600 MHz signal, the counter counts down from a binary value of 111111, which effectively multiplies the 9.375 MHz signal by 64.
		The pll is locked when the input voltage to the VCO reaches a steady value.
	www-unix.ecs.umass.edu /~djasinsk/cdpll.html (1420 words)

	Phase-Locked Loop Tutorial, PLL
		There has been traditionally some reluctance to use PLL's, partly because of the complexity of discrete PLL circuits and partly because of a feeling that they cannot be counted on to work reliably.
		Thus, in a PLL with type I phase detector, the loop filter acts as a low-pass filter, smoothing this full-swing logic-output signal.
		Most PLL designs, especially for synthesizers where third and fourth order loops are common, use a different terminology, and deal mainly with the open loop gain and phase.
	www.uoguelph.ca /~antoon/gadgets/pll/pll.html (3369 words)

	SourceForge.net: pointless-devel
		In the future one may maybe choose PLL for simple presentations and python for advanced presentation.
		.pll: ------------------------------------------ =item this item spans multiple lines and it is even allowed to =item now here comes the second item ------------------------------------------ On one hand, I"m against giving semantical meaning to white-spaces but on the other hand, I"m a fan of Huffman and wishes to compress my keystrokes as much as possible, i.e.
		This file will (as a start) contain the thoughts about PLL and the parser and it will be updated as we move along (famous last words).
	sourceforge.net /mailarchive/message.php?msg_id=7263676 (1777 words)

	Possible Causes for PLL Loss of Lock
		Switching noise on the inputs is a form of deterministic jitter that is subject to the input jitter specification shown in the device family datasheet.
		The PLL could lose lock during or after PLL reconfiguration if the M counter, N counter or phase shift settings have changed during the reconfiguration process. Changes to the post-scale counters do not affect the PLL lock signal.
		The PLL output will continue to toggle at the last frequency but will drift to a lower frequency (or higher, depending on the clock setting). The PLL could lose lock since the output clock phase (and frequency) will have drifted outside of the lock window of the PLL.
	www.altera.com /support/devices/pll_clock/basics/pll-loss-lock.html (610 words)

	The Phase-Locked Loop (PLL) page
		The Phase-Locked Loop (PLL) is a closed loop frequency control system functioning of which is based on the phase sensitive detection of phase difference between the input signal and the output signal of the controlled oscillator (CO).
		The PLL has found use since the beginning of the 1930-ies [Bellescise, 1932].
		In applications the PLL system is often used in combination with the automatic frequency control (AFC) system and/or automatic gain (or signal level) control system.
	elve.le.ttu.ee /min_www_home/PLLoop/PLL-PAGE.HTM (457 words)

	Circuit Sage: Phase Locked Loop Tools and Links
		PLL Design Assistant, from Mike Perrott at MIT, software for allows fast and straightforward design of PLLs at the transfer function level.
		National's PLL Design Software: A change from their old routine to be much more powerful and completely web based.
		PLL design one, two, three by Mark Curtin and Paul O'Brien at Analog Devices.
	www.circuitsage.com /pll.html (776 words)

	Bandwidth stabilized PLL - Patent 6590950
		The PLL of claim 11, wherein said pilot determining means includes a low pass filter for removing said data.
		This invention relates generally to PLLs (phase locked loops) and specifically to PLLs that are used in FPLLs (frequency and phase locked loops) that have an I (in-phase) channel, including a demodulated pilot, and a Q (quadrature) channel.
		The PLL has a bandwidth that is dependent upon pilot level and is therefore sensitive to noise and other channel impairments (such as a "ghosted" 180.degree.
	www.freepatentsonline.com /6590950.html (2499 words)

	What is PLL? - A Word Definition From the Webopedia Computer Dictionary
		A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate and demodulate a signal and divide a frequency.
		PLL is used often in wireless communications where the oscillator is usually at the receiver and the input signal is extracted from the signal received from the remote transmitter.
		GlobalSpec.com: PLL Frequency Synthesizers - Provides database of suppliers for PLL Frequency Synthesizers.
	www.webopedia.com /TERM/P/PLL.html (156 words)

	Performance of the MAX2395 PLL with 80kHz Comparison Frequency - Maxim/Dallas
		Due to its internal architecture, the RF output frequency is at 5/6 of the RF LO frequency, which is generated from an on-chip integer-N PLL.
		So the comparison frequency used by the MAX2395's PLL needs to be reduced to a number whose multiple is 240kHz and 13.0/26.0MHz.
		The EVM (error vector magnitude) will be also degraded, since the PLL contribution to EVM is roughly proportional to its integrated phase error.
	www.maxim-ic.com /appnotes.cfm/appnote_number/2009/ln/en (532 words)

	CEVA, Inc. - PLLXpert (Site not responding. Last check: )
		PLLXpert, an automated PLL compiler technology has transformed analog PLL design and delivery though enabling digital and analog designers to rapidly design robust clock synthesizers on a range of standard CMOS processes.
		The PLLs generated are based on a silicon proven architecture tried and tested in various calibration chips over six process generations.
		To ensure risk-free PLLs, each silicon process has been verified by a companion PLL compiler calibration chip which validates the extremes of the design range.
	www.pllxpert.com /technology/index.php (460 words)

	PLL Synthesizers : FUJITSU EMEA
		The Fujitsu PLLs utilise state-of-the-art BiCMOS RF processes and are designed to be used as frequency synthesisers for local oscillators in modern radio systems.
		The product range features modern RF packaging technology ranging from traditional SSOP to specialised Bump Chip Carrier (BCC), of which the BCC-16 provides an area saving of up to 50% compared to SSOP devices coupled with enhanced RF performance.
		Frankfurt, August 8, 2003 – Fujitsu Microelectronics Europe has announced the MB15F7xUV series, a new family of sub-miniature dual PLL frequency synthesisers designed for the high frequency mobile communications market.
	www.fujitsu.com /emea/services/microelectronics/pll (178 words)

	LAB736 - Dynamics of a PLL Timebase
		The response of the PLL is delayed as shown by the shift to the right of both the frequency (Trace C) and phase (interval error) waveform (Trace A).
		It is obvious by the similarity of the PLL output frequency and the control voltage waveforms that the VCO is tracking the control voltage very precisely.
		The PLL is originally operating with an output frequency of 400 MHz.
	www.lecroy.com /tm/library/labs/lab736/default.asp?menuid=2 (645 words)

	Eagleware-Elanix \| PLL (Site not responding. Last check: )
		PLL includes sophisticated algorithms which model the true non-linear behavior of phase-locked loops.
		It is the only program you’ll need to design phase-locked loops for synthesizers, phase modulators and demodulators, frequency modulators and demodulators, and other applications.
		Input tabs for creating a design are on the left and output tabs for viewing data are on the right.
	www.eagleware.com /products/genesys/pll.html (69 words)

	LAB1007 - Phase Locked Loop Basics
		If the PLL is to acquire and track a signal the bandwidth of the loop filter will be greater than if it expects a fixed input frequency.
		Once the PLL is locked and tracking a signal the range of frequencies that the PLL will follow is called the tracking range.
		This PLL is used in a frequency synthesizer and shows the response to an 80 kHz step in the 10 MHz reference input.
	www.lecroy.com /tm/library/LABs/LAB1007/default.asp (774 words)

	Minutes of PLL 1998-1999 Executive Committee Meeting, July 17, 1999
		The hope is that PLL will continue to work on publicizing itself to other groups, thereby raising our perceived value.
		PLL did not get any programs accepted this year, and it seems that there is an erosion of interested in PLL at ALA, and our reciprocal agreement that we have maintained in the past for a free booth at each other’s annual meeting may not continue.
		Holly Mohler read the Secretary’s report and there was a brief discussion about changing the PLL bylaws, so that the election ballots could be done in a more economic fashion than they currently are.
	www.aallnet.org /sis/pllsis/minutes/minutes99-1.html (760 words)

	Broadcast Warehouse LCD PLL FM Exciter Kit Review
		The PLL is implemented with the popular Motorola MC145170 PLL frequency synthesiser IC (MC145170 data sheet (PDF format) - 382Kb).
		Compare this with the Broadcast Warehouse 1W PLL, where the PLL loop filter is passive, and the range is limited to the +5V supply to the PLL chip.
		Note this is different from Broadcast Warehouses' 1W tuned PLL unit, as in that unit the loop components are driven from an on-board +5V regulator.
	www.irational.org /sic/radio/bc-ware-lcd-pll.html (2877 words)

	Electronics 12
		However, the PLL must be able to respond to changes, so the corner frequency should be above the frequency of those changes.
		The PLL is a frequency-to-voltage converter of a different type than we have met before.
		A useful device that uses a PLL is the 567 tone detector.
	www.du.edu /~etuttle/electron/elect12.htm (3473 words)

Try your search on: Qwika (all wikis)