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Topic: PMOS

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	[No title]
		PMOS transistor P6 comprises a source connected to the power supply voltage VDD, a gate and a drain, both being connected to the second node n5 where a complementary output signal CSAB is output.
		PMOS transistors P5 and P6 are turned on when voltage differences between the power supply voltage VDD and each of the nodes n4 and n5 are greater than threshold voltages of the PMOS transistors P5 and P6, respectively.
		PMOS transistors P5 and P6, each with a source connected to a power supply voltage, step up the voltage of the nodes n4 and n5, while the PMOS transistors P7 and P8, each with a source connected to an input signal line, step down the voltage of nodes n4 and n5.
	www.people.fas.harvard.edu /~arcrock/spl/spl_gui/spec.txt (4471 words)

	Adjustable trigger voltage circuit for sub-micrometer silicon IC ESD protection - US Patent 6577480 (Site not responding. Last check: 2007-10-09)
		A second PMOS transistor and a second NMOS transistor are connected in series between the Vss line and the Vdd line with the PMOS transistor having a gate connected to the junction between the first PMOS transistor and the first NMOS transistor and the second NMOS transistor having a gate connected to the Vdd line.
		The gate 88 of the PMOS transistor 74 is connected to the junction between the drain 64 of the PMOS transistor 58 and the drain 66 of the NMOS transistor 60.
		The gate 112 of the PMOS transistor 106 is connected to the junction between the NMOS transistor 102 and the NMOS transistor 104.
	www.patentstorm.us /patents/6577480.html (2704 words)

	United States Patent Application: 0040140841
		PMOS 21, 22 are connected in series between the high voltage electricity source VDD and output node N2.
		PMOS 41 is connected between the high voltage VDD and the output node N4.
		Since, gate electric potential of PMOS 51p, 52p is connected with the electric potential of low voltage level, the voltage impressed between gate and source or between gate and drain is not higher than the low voltage level.
	appft1.uspto.gov /netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20040140841".PGNR.&OS=DN/20040140841&RS=DN/20040140841 (10988 words)

	United States Patent Application: 0040196698
		The PMOS structure 30 is formed on an N-well 18 and comprises a PMOS floating gate 34, a P.sup.+ source region 20, and a P.sup.+ drain region 22.
		The PMOS transistor 101 comprises a select gate 301, a P.sup.+ source region 201, and the P.sup.+ doping region 202 acting as a drain of the PMOS transistor 101.
		The PMOS transistor 102 is a floating gate transistor comprising a P.sup.+ poly floating gate 302, a P.sup.+ drain region 203, and the P.sup.+ doping region 202 acting as a source of the PMOS transistor 102.
	appft1.uspto.gov /netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20040196698".PGNR.&OS=DN/20040196698&RS=DN/20040196698 (2596 words)

	[No title] (Site not responding. Last check: 2007-10-09)
		According to another aspect of the present invention, N-wells for isolating the PMOS intermediate transistors are tied to upwardly vertically adjacent intermediate voltages for the shared bias embodiment and are tied to upwardly vertically adjacent NMOS bias voltages for the split bias embodiment.
		A high-voltage level shifter as in claim 2, wherein the PMOS non-inverted output drain is coupled to the PMOS inverted output gate; and wherein the PMOS inverted output drain is coupled to the PMOS non- inverted output gate.
		A high-voltage level shifter as in claim 11, wherein the PMOS non-inverted output drain is coupled to the PMOS inverted output gate; and wherein the PMOS inverted output drain is coupled to the PMOS non- inverted output gate.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=98/35444.980813&ELEMENT_SET=DECL (6633 words)

	PMOS morning briefing - 19 May
		The PMOS said it was important to be clear about where we were in the process.
		The PMOS drew journalists' attention to an extract from a speech given by the Foreign Secretary in Brussels today in which he had said, "It's absurd to suggest, as some in Britain and elsewhere do, that the Europe of twenty-five will be a tyranny, when this wider Europe has been built on tyranny's defeat.
		Asked about asylum policy, the PMOS said that we were in favour of co-operation on asylum because co-operation was the key to tackling a problem which, by its very nature, involved more than one country.
	www.number-10.gov.uk /output/Page3726.asp (2034 words)

	[No title] (Site not responding. Last check: 2007-10-09)
		The second PMOS transistor is connected with its source and bulk contacts to the interconnection point between a gate contact of the first PMOS transistor and a drain contact of a third PMOS transistor and to a drain contact of a fourth PMOS transistor and with its gate contact to a voltage node.
		The third PMOS transistor is connected with its bulk contact to said first supply voltage terminal, with its source contact to an interconnection point between a gate contact of the fourth PMOS transistor and a drain contact of a fifth PMOS transistor and with its gate contact to a first control voltage node.
		The PMOS transistor M6 is connected with its source and bulk contacts to a voltage node X and with its gate contact to a voltage node E. In the embodiment in Fig.
	www.wipo.int /cgi-pct/guest/getbykey5?KEY=03/107532.031224&ELEMENT_SET=DECL (3522 words)

	Opinion: There's a reason IT PMOs fail
		From a bad start, many PMOs take the next step in being annoying: they try to tell project teams "how they must report to meet management's expectations," they harangue the teams to use "standards," and they ask for additional reports the teams hadn't planned to provide.
		And that one thing is looking at the PMO from the perspective of the project teams first, and management second.
		Dig in, do the grunt work and don't expect the teams to produce anything for the PMO that you wouldn't want to produce yourself if you were in their position, and don't ask for anything that doesn't have a direct benefit to the project itself.
	www.itworld.com /AppDev/1251/020410itpmo/search.html (818 words)

	Downing Street Says...: European Constitution
		Asked to explain why a referendum could not be held on the basis of the Constitution agreed in June, the PMOS said that in the Government's view, Parliamentary scrutiny - and therefore the role of Parliament - was important.
		Asked if the Prime Minister continued to believe that the draft Constitution was simply a 'tidying up exercise', the PMOS said the Prime Minister continued to believe that the draft Constitution was an essential part of the enlargement process for Europe which did not threaten this country's basic position.
		Asked for a reaction to reports that the Prime Minister had discussed the issue of a referendum with Rupert Murdoch, the PMOS said that he was not aware of any such discussions having taken place.
	www.downingstreetsays.org /archives/000445.html (2306 words)

	PMOS morning briefing - 8 March
		Put to him that it should be done in public, the PMOS said that in the first instance it was right for Ministers to enquire of their Department about the allegations that had been made.
		The PMOS also took the opportunity to point out that Professor King had held a press conference at the conference in Seattle, where the memo had reportedly been discovered, with an unrestricted QandA.
		Asked for a reaction to the latest Peter Foster claims, the PMOS said that as we had made clear at the weekend, we were not going to dignify the allegations by responding to them.
	www.number-10.gov.uk /output/Page5470.asp (1450 words)

	United States Patent: 6,674,672 (Site not responding. Last check: 2007-10-09)
		The memory device of claim 7, wherein the drain of the PMOS compensation transistor is coupled to an n-well of the at least one PMOS target transistor in p-type wafer technology to regulate a threshold voltage of the at least one PMOS target transistor.
		The memory device of claim 7, wherein the drain of the PMOS compensation transistor is coupled to a substrate of the at least one PMOS target transistor in n-type wafer technology to regulate a threshold voltage of the at least one PMOS target transistor.
		The memory device of claim 10, wherein the drain of the PMOS compensation transistor is coupled to a substrate of the at least one PMOS target transistor in n-type wafer technology to regulate the threshold voltage of the at least one PMOS target transistor.
	web.engr.oregonstate.edu /~flf/6674672.html (7429 words)

	Antisense Phosphorodiamidate Morpholino Oligomer Length and Target Position Effects on Gene-Specific Inhibition in ...
		to 95% and 5' truncated PMOs inhibited luciferase from 6 to
		All PMOs targeted to myc-luc (Table 1), except PMOs 214, 215, 327, 328, 333, and 334, were analyzed by comparing the inhibition of luciferase in cell-free reactions with the PMO 2° score (Table 1).
		the PMO, as exemplified by the inhibition with PMOs 326, 208,
	aac.asm.org /cgi/content/full/49/1/249 (4157 words)

	The CMOS Inverter Explained
		The PMOS device is in the linear region (VSD<=VSG+VTP).
		The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vo+VTP).
		The PMOS device is cut off when the input is at VDD (VSG=0 V).
	www.ee.calpoly.edu /~dbraun/courses/ee307/F02/02_Shelley/Section2_BasilShelley.htm (1149 words)

	United States Patent: 6,556,068 (Site not responding. Last check: 2007-10-09)
		The integrated circuit differential amplifier of claim 7, wherein the drain of the PMOS compensation transistor is coupled to a substrate of the at least one PMOS target transistor in n-type wafer technology to regulate a threshold voltage of the at least one PMOS target transistor.
		The integrated circuit differential amplifier of claim 18, wherein the drain of the PMOS compensation transistor is coupled to both the backgate of the first PMOS transistor and the backgate of the second PMOS transistor to regulate a threshold voltage of the first and second PMOS transistors.
		The integrated circuit differential amplifier of claim 18, wherein the drain of the PMOS compensation transistor is coupled to a substrate of the first PMOS transistor and the second PMOS transistor in n-type wafer technology to regulate a threshold voltage of the first and the second PMOS transistors.
	web.engr.oregonstate.edu /~flf/6556068.html (6312 words)

	Downing Street Says: the Prime Minister's Official Spokesman, uncut and annotated by you
		Asked about the rest of the reshuffle, the PMOS said that as they could see the Prime Minister was preoccupied with other things, but no doubt it would be before too long once other things were out of the way....
		Put to the Prime Minister's Official Spokesman (PMOS) that the Prime Minister had said that he would be consulting allies regarding Iran, and was there anything further to be added, the PMOS said that first of all, we regarded Kofi...
		Asked about the summit, the PMOS said it was very much about debating the issue of how the EU met the challenge of globalisation in order to get the priorities right in the EU before we got to the December...
	www.downingstreetsays.org (3569 words)

	Lecture 3 Notes: (Site not responding. Last check: 2007-10-09)
		Notice that PMOS tree has two connections that are never possible.
		PMOS tree replaced with one PMOS with gate tied to Vss.
		Pull-up tree is a “cross-coupled” pair of PMOS transistors.
	www.engin.brown.edu /courses/En160/lecture_notes/Lec_3_notes.class.htm (1388 words)

	PMOs struggle to balance project discipline, bureaucracy - Computerworld
		But as PMOs go about establishing more disciplined approaches to project management, their leaders are discovering how tough it is to strike a balance between creating structure and excessive bureaucracy.
		Several PMO managers said one way to achieve buy-in with IT project managers is to start a PMO slowly and build on project successes to gain their trust.
		Since it established a PMO in December 2002, the state of Florida's Department of Health division of information technology "hasn't had any 'fl hole' projects and that is a success for a government agency," said Jane Matthews, a project manager for the group in Tallahassee.
	www.computerworld.com /managementtopics/management/project/story/0,10801,101378,00.html?source=x10 (1279 words)

	PMOs: Projects in Harmony
		At the other end of the spectrum are mature PMOs where traditional project issues (resource management, project prioritization, planning and tracking, project risk management, and the like) are coordinated to generate better economies of scale along with vendor, training, procurement, outsourcing, and risk management at the corporate level.
		The PMO is more a label applied to the group of PMs that are available to the myriad of initiatives tasked to the IT organization.
		Since the PMO is all about management, the transition to Level 2 is a strategic inflection point since it indicates stability.
	www.gantthead.com /article.cfm?ID=7149 (1460 words)

	PMOS morning briefing - 21 April
		Asked for a reaction to reports that British troops going to the scene of the attacks had been stoned, the PMOS said that he was not aware of the full detail of the incident at this stage. However, as he understood it, the situation had been brought under control very quickly.
		Asked for a reaction to the criticism of the Government expressed by the Archbishop of Canterbury yesterday, the PMOS said that he had nothing to add to what had already been said about this matter.
		Asked if the Government believed that Abu Hamza should receive legal aid, the PMOS said that since Abu Hamza was on the UN Security List as an Al Qaida associate, he needed to apply to the Treasury for a special licence to receive legal aid. We were unable to comment until that was done.
	www.number10.gov.uk /output/Page5681.asp (226 words)

	PMOS Revisited (ResearchIndex)
		Abstract: The Persistent Mature Object Space, PMOS, garbage collection algorithm is designed to incrementally collect all garbage in a potentially large persistent object store.
		The goal of the PMOS algorithm is to break the collection of garbage into small enough units so that disruption to the running system is insignificant.
		PMOS is able to collect the small units in arbitrary orders whilst eliminating cyclic garbage and being able to guarantee progress.
	citeseer.ist.psu.edu /325170.html (307 words)

	Connecting PMOS and NMOS
		Yet based on our original signal flow diagram, it is more desirable to place the PMOS transistor directly on top of the NMOS transistor- for a more compact layout.
		After we have picked the reference point, the outline of the shape will appear attached to the cursor and we will be able to move the shape around.
		The PMOS transistor was placed within the n-well, this well also has to be biased with the VDD potential.
	www.ee.siue.edu /~gengel/prasad/cnntpn.htm (1598 words)

	PMOS: A Complete and Coarse-Grained Incremental Garbage Collector for Persistent Object Stores - Eliot, Moss, Munro, ...
		The size, complexity, and permanence characteristics of a persistent object store mean that an automatic storage reclamation system, in addition to ensuring that all unreachable and only unreachable data is reclaimed, must also maintain store consistency while limiting I/O overhead when collecting secondary-memory data.
		The initial implementation of Lumberjack is proceeding in parallel with the writing of this paper and serves a number of purposes:...
		PMOS: A complete and coarse-grained incremental garbage collector for persistent object stores.
	citeseer.ist.psu.edu /moss96pmos.html (510 words)

	Manual Layout PMOS (Site not responding. Last check: 2007-10-09)
		Note that the PMOS transistor will also be surrounded by the N-well region.
		For the PMOS transistors however a different approach must be taken: A larger n-type region (n-well) must be created, which acts like a substrate for the PMOS transistors.
		From the process point of view, the n-well is one of the first structures to be formed on the surface during fabrication.
	www.ee.siue.edu /~gengel/prasad/pmos.htm (293 words)

	Strained Silicon and Transistor Performance - Technology & Research at Intel (Site not responding. Last check: 2007-10-09)
		In PMOS (P for positive) devices, the signal carriers are "holes," or an absence of electrons.
		The current in a PMOS transistor flows opposite to that of an NMOS transistor.
		Intel's implementation of strained silicon devices improves drive current about a 25 percent in PMOS and about 10 percent in NMOS in silicon manufactured with it 90nm process.
	www.intel.com /technology/silicon/si12031.htm (936 words)

	Physical Sciences - 60nm - pMOS nano-transistor
		In particular, boron penetration from the gate electrode through the gate oxide into the channel, and enhanced diffusion of boron from the source and drain regions due to defects introduced during ion implantation threaten pMOS viability.
		The vertical (55nm) and lateral (30nm) extent of the lightly doped drain and source regions under the polysilicon gate, as well as the heavily doped drain, source (80nm) and gate electrodes are apparent.
		The 20nm channel is clearly indicated in the micrograph and provides us with incontrovertible evidence that a sub-100nm pMOS technology utilizing hyper-thin gate oxides and ultra-shallow junctions is viable provided that the thermal budget is less than 1000C for 10 seconds and ultra-low energy implants (<1keV) are used.
	www.bell-labs.com /org/physicalsciences/projects/60nm/60nm2.html (197 words)

	PMOS Help Desk (Site not responding. Last check: 2007-10-09)
		PMOS Help Desk (PHP MySQL Open Source) was previously sold as the InverseFlow Help Desk.
		The software has now been open-sourced and can be downloaded and distributed freely under the GNU public license.
		The only requirement of using this software is you must retain the "Powered by PMOS Help Desk" link on the product.
	www.h2desk.com /pmos (194 words)

	Transistor - Encyclopedia.WorldSearch (Site not responding. Last check: 2007-10-09)
		Another leap in miniaturisation came when complete circuits were integrated on to tiny silicon chips.
		The invention of metal oxide silicon (MOS) transistors by the Radio Corporation of America (RCA) in 1960, led to the development of PMOS and NMOS chips that integrated more functions, used less power and were cheaper, but were slower than BJT types.
		They followed this in 1968 by producing complementary metal oxide silicon CMOS chips that were faster and used even less power.
	encyclopedia.worldsearch.com /transistor.htm (4943 words)

	[No title] (Site not responding. Last check: 2007-10-09)
		PMOS should be three times wider that NMOS.
		This bias circuit consists of PMOS and NMOS cascaded mirror circuit.
		PMOS should be very narrow and gate is connected to ground, such that it is always ON and drips very small current.
	www.public.asu.edu /~mpradeep/project1_report_eee523.doc (1211 words)

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