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| | POWER3: Next Generation 64-bit PowerPC Processor Design |
 | | The POWER3 microprocessor objectives were to continue the POWER2 architecture tradition of bringing real solutions to IBM RISC System/6000 customers' high compute needs, while adding 64-bit addressability, double-word interger operations, and symmetric multiprocessor support in the PowerPC Architecture. |
 | | Using IBM packaging technology's high I/O count, the POWER3 processor was implemented with separate, independent 16 byte memory bus and 32byte L2 bus, each with separate address, data, and control lines, achieving 6.4GBps to the L2 at 200 MHz. |
 | | Second, the POWER3 processor implements sequential instruction and data access detection algorithms in hardware, which permit the prefetch of cache lines to closer levels of the memory hierarchy. |
| www-1.ibm.com /servers/eserver/pseries/hardware/whitepapers/power3wp.html (2347 words) |
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