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	IBM POWER4 Processor Review
		The POWER4 consists of 2 identical processor cores which implement PowerPC AS instruction set, the die measures about 400 mm2, it's based on the 0.18 micron copper SOI IBM CMOS 8S2 technology with 7 metallization layers, works at 1.1 and 1.3 GHz, and is the fastest microprocessor for today.
		The L1 cache is capable of delivering to the front part of the pipeline up to 8 instructions per clock according to the address given by the IFAR register the contents of which is determined by the branch prediction unit.
		The POWER4 has a hardware prefetch unit which loads data into the L1 cache from the whole memory hierarchy, and there are instructions which allow controlling this process on a software level.
	www.digit-life.com /articles/ibmpower4 (2285 words)

	The circuit and physical design of the POWER4 microprocessor
		The POWER4 chips were fabricated in the state-of-the-art IBM 0.18-µm CMOS 8S3 SOI (silicon-on-insulator) technology with seven levels of copper wiring [4].
		At the start of the POWER4 microprocessor design, a tool suite and methodology were put together by picking the best elements of established IBM microprocessor design methodologies, such as POWER3, S/390* G4, and PowerPC 615 [6, 7], and combining them with new ideas specific to this design.
		For a total POWER4 chip power of ~115 W and a maximum transient power change of ~25 W, it was necessary to embed 250 nF of decoupling capacitance into critical areas of the chip.
	www.research.ibm.com /journal/rd/461/warnock.html (11661 words)

	How IBM plans to change the chip world \| Tech News on ZDNet
		Power4 chips will combine two processors on a single die -- the slab of silicon on which the processor is built.
		Power4 is also a 64-bit chip, meaning it processes data in 64-bit chunks, unlike most desktop chips, which tackle data in 32-bit chunks.
		Power4 is on schedule to ship in the second half of next year in IBM's RS/6000 Unix servers and its AS/400 servers for small and medium-size businesses running Unix or Linux.
	news.zdnet.com /2100-9595_22-519189.html (860 words)

	IBM Arms p630 Server with Power4+ Chips
		Karl Freund, vice president, IBM eServer pSeries, claimed the addition of the Power4+ chip will make the p630 the most powerful entry-level 4-way server on the market, with as much as three and a half times the performance of a comparable machine from Sun Microsystems.
		Freund said putting Power4+ chips on the p630 is a continuation of IBM's play to offer an attractive "price/performance equation." He said a 4-way eServer p630 set an industry record in recent benchmark tests for entry-level systems, supporting 1,988 simultaneous connections, compared to the 568 connections registered by the 4-way Sun Fire v480.
		Power4+ chips are designed via the 0.13 micron fabrication process and contain more than 180 million transistors.
	www.serverwatch.com /news/print.php/1592901 (570 words)

	POWER4 - Wikipedia, the free encyclopedia
		The POWER4 chip is a computer processor that implements the IBM POWER and 64-bit PowerPC instruction set architectures.
		Released in 2001, the POWER4 chip is based on the previous POWER3 chip design.
		The POWER4 chip is a multicore chip, including two PowerPC cores.
	en.wikipedia.org /wiki/POWER4 (347 words)

	POWER4 System Microarchitecture
		POWER4 was designed from the outset to satisfy the needs of both of these systems.
		With POWER4, we accepted the principle that one does not achieve high levels of reliability by only choosing reliable parts and building error correction codes (ECC) into major arrays, but an approach that eliminated outages and provided redundancy where errors could not be eliminated was required.
		But, with the POWER4 architecture, this is also where we would natively attach an interface to a switch for clustering multiple POWER4 nodes together.
	www.ibm.com /servers/eserver/pseries/hardware/whitepapers/power4.html (1871 words)

	IBM Arms p630 Server with Power4+ Chips
		Freund said putting Power4+ chips on the p630 is a continuation of IBM's play to offer an attractive "price/performance equation." He said a 4-way eServer p630 set an industry record in recent benchmark tests for entry level systems, supporting 1,988 simultaneous connections, compared to the 568 connections registered by the four-way Sun Fire V480.
		IBM officials said it will be four times faster than the Power4 and will be available in both high- and low-end systems by the end of 2004.
		The p630 with Power4+ runs the AIX and Linux operating systems and will be available February 28, starting at $19,025.
	siliconvalley.internet.com /news/print.php/1592401 (569 words)

	IBM Research \| Projects \| VLSI Design ! Power4 Design \|
		Power4 is the processor that will be used in the next-generation RS/6000 and AS/400 systems (IBM eServer i-series and p-series).
		The Power4 chip is divided into 12 units, some of which are being designed by multi-site teams.
		The Research team focuses on all aspects of VLSI design as well as design tools and methodologies.
	www.research.ibm.com /power4 (167 words)

	Real World Technologies - A Big Blue Shadow over Alpha, SPARC, and IA-64
		With the recent disclosure of detailed information about the processor core of the POWER4 server MPU at Microprocessor Forum 2000, it appears IBM is preparing to leapfrog its way to preeminence in the 64 bit MPU market within the next 12 months.
		In addition, the POWER4 device integrates controller logic for external L3 cache and main memory, along with interprocessor communications channels for a total chip complexity of about 170 million transistors.
		The four POWER4 devices within the MCM are placed such that the two chip edges with the inter-chip communication drivers are facing inwards.
	www.realworldtech.com /page.cfm?ArticleID=RWT101600000000 (420 words)

	IBM Power4 System User Guide
		All the nodes employ the same 1.3GHz IBM Power4 microarchitecture, run the same AIX 5.1 operating system, and all are connected through an IBM high-speed switch (SP Switch2).
		The architectural features of the Power4 chip are designed with a high memory bandwidth to accommodate the superscalar operations of a 1.3 Gigahertz processor.
		Since this integrated system is very heterogenous in nature by the different characteristics of the Power4 nodes in the configuration, a number of different options of node combinations may be possible for a given job description.
	www.tacc.utexas.edu /resources/user_guides/regatta (11457 words)

	CSE - The IBM Power4 Processor: Overview and Initial Experiences
		Each POWER4 HPC processor chip contains one core, rather than two, and the L2 cache is dedicated for the core.
		A full description of the POWER4 architecture is beyond the scope of this article, for further details see the references [1,2].
		The latter is of some concern, although this effect is not peculiar to the power4 processor, for it has been evident in all previous power-based CPUs from IBM.
	www.cse.clrc.ac.uk /arc/power4.shtml (1244 words)

	G5 or POWER4 - Applelinks Mac Boards (Site not responding. Last check: 2007-10-12)
		The POWER4 processor is already dual core and it integrates switch based bandwidth control without an additional controller.
		Initially IBM was only supposed to be releasing them in their highest end mainframe servers, but that story has changed and now they are going to be implementing the POWER4 in all lines except their lowest end servers; and the Wintel consumer boxes they make.
		Considering that the POWER4 is really a "G" processor on steroids, using the same RISC instructions, but designed for multi-threading out the booty, IBM could easily implement AltiVec.
	www.applelinks.com /boards/Forum25/HTML/000017.html (1894 words)

	Geek.com IBM Power4 and Power4+ Processor Table (Site not responding. Last check: 2007-10-12)
		The Power4 was initially produced on a.18 micron Silicon-on-Insulator 7-layer process with copper interconnect technology.
		The Power4 has a chip to chip bus at 1/2 the clock rate of the chip.
		IBM cut the size and power utilization of the Power4 chips with the 1.45 and 1.2GHz models by moving them to a.13 micron process.
	www.geek.com /procspec/ibm/power4.htm (118 words)

	Macs to Get Real POWER? - OSNews.com
		According to a brief paragraph on MacOS Rumours Apple may be switching to IBM POWER4 CPUs instead of the Motorola G5 for future Macs.
		POWER4 CPUs in the future they couldn't have made a much better choice if they want performance.
		Currently the POWER4 ships in a multi-CPU module consisting of 4 chips and a separate L3 cache.
	www.osnews.com /story.php?news_id=1357 (514 words)

	CommsDesign - IBM plans 500-MHz bus for Power4 processor (Site not responding. Last check: 2007-10-12)
		IBM uses a technology known as a synchronous wave-pipelined interface, or an elastic interface, for the Power4 I/O. The key is controlling latency.
		Though the Power4 is not yet in production, IBM has a test chip running in the lab.
		A Power4 called the Pulsar, which is to be launched in IBM's RS/6000 servers, will be produced at the 0.18-micron level, with copper.
	www.commsdesign.com /showArticle.jhtml?articleID=18302433 (609 words)

	Geek.com Geek News - IBM's Power4 Gigaprocessor (Site not responding. Last check: 2007-10-12)
		The Power4 chips and the PowerPC chips are not the same.
		But The power4 is a server chip that (as I recall,) costs $5000 per chip runs at 150 watts and requires a special bus system.
		90% of the transistors of Power4 are cache.
	www.geek.com /news/geeknews/2001may/bch20010518005971.htm (431 words)

	Power4 from Fox and Cooper
		Power4 from Fox and Cooper has acquired an enviable reputation for its innovative approach to providing generators and temporary power distribution equipment.
		Following an incident at the Corus Steelworks in Scunthorpe, Power4 was mobilized to supply 800kVA of power.
		Within 2 hours of receiving the call the set was delivered, installed and was up and running to enable the Corus staff to restore power to the plant.
	www.power4.biz /index.htm (87 words)

	IBM unveils next-generation Power4 CPU (Site not responding. Last check: 2007-10-12)
		The Power4 will be used in both the AS400 and RS6000 system families, which are planned to hit the market in 2001.
		The Power4 is the first IBM processor design to include two processors and an L2 cache on the same die, taking advantage of the transistor densities possible with 0.18-micron design rules.
		It is an all-digital design, with low power, source-terminated drivers and active clamps on the receiving circuits, where a FIFO is placed.
	www.hoise.com /primeur/99/articles/monthly/AE-PR-09-99-60.html (546 words)

	IGM: Power4-based chip May Give Insight into Next-Generation Apple CPU
		Power4 - like the early PM G4/350 - might give Apple the marketing edge it sorely needs while it competes with the next-generation Intel/AMD chips.
		To be able to use Power4 in a 32-bit environment while it waits for the OS to catch up may prove a temptation for Apple that is too great to ignore.
		It has been described a processor which is a derivative of the Power4, meaning it shares some design ideas.
	www.insanelygreatmac.com /news.php?id=1086 (890 words)

	IBM demos BladeCenter using future Power4 variant \| The Register
		As it turns out, sticking with the future Power4 chips for AIX blades will probably be a much smarter move for the long run.
		It clocks higher and runs cooler than current Power4 chips, and it is widely expected to be used in Apple Macs and in entry pSeries servers supporting Linux and AIX operating systems.
		IBM could have another derivative of the Power4 chip in the works, too, that we have not yet heard of.
	www.theregister.co.uk /2002/10/29/ibm_demos_bladecenter_using_future (1012 words)

	CMP resources: Press releases, academic papers, and presentations on dual-core and multicore processors
		IBM to unveil Power4 processor at Hot Chips by David Lammers.
		Power4 vs. Itanium 2: "Madison" Takes the Lead published by Cambridge Consulting.
		The report concludes that the Itanium 2 processor outclasses the Power4, although this study was probably funded by HP or Intel.
	www.princeton.edu /~jdonald/research/cmp (3566 words)

	TACC > Single Processor Optimization on the IBM Power4 System
		When the two loops shown above are timed on the IBM Power4, the code with stride-1 access takes 37 clock periods per iteration while the non-unit stride example requires 198 cycles per iteration.
		Consider what happens when this code is run on the IBM Power4 system, which has a 16 KB, two-way set associative L1 data cache.
		Programmers that code for the IBM Power4 system are encouraged to use their optimized libraries: ESSL/PESSL, MASS, and libxlopt.a.
	www.tacc.utexas.edu /resources/userguides/power4/optimization (4582 words)

	PCQuest : Server Side : High-end Servers: IBM’s Power4-based Servers
		The Power4 series places two complete CPU cores on a single chip, speeding it up and adding high-speed connections to a max of three other pairs of Power4 CPUs.
		To communicate with Power4 chips on other modules, there are two 8-byte buses: one on the chip and one off the chip operating at half the speed of the processor.
		L1, L2 caches and directories on the Power4 chip are manufactured with spare bits in their arrays which can be accessed via programmable steering logic to replace faulty bits in the respective arrays.
	www.pcquest.com /content/search/showarticle.asp?artid=45410 (775 words)

	GRIDtoday: NEW IBM SOFTWARE COMBINES WEBSPHERE + LINUX + POWER4 CHIP
		As more banks, retailers, manufacturers, government agencies and others turn to Linux as a reliable environment for critical applications, they want to complement and expand its use to more powerful servers able to handle large workloads.
		IBM also announced that the WebSphere software will be included in a new offering from IBM Global Financing that allows qualified customers in the United States and Canada to defer payments until January 2004 at no charge or choose special low financing rates.
		Running Linux on POWER4 enables administrators to take advantage of the wealth of applications available for Linux while leveraging the considerable performance and scalability of an enterprise-level environment.
	www.gridtoday.com /03/0714/101688.html (588 words)

	IBM expands lineup for Linux on Power4 - ZDNet UK News
		The move, announced on Wednesday, begins to flesh out the software portfolio that will be necessary if IBM is to succeed in its goal of making Linux popular on its full server line; Linux currently is most frequently found only on servers that use Intel processors.
		IBM is working to spread the Power4 processor across its entire server line.
		The new edition of WebSphere for Linux on Power4 systems will be available from 15 July, when the company ships version 5.02, IBM said.
	news.zdnet.co.uk /software/0,39020381,2137343,00.htm (453 words)

	Microprocessor Watch #34; 1/27/2000
		Cahners MicroDesign Resources today announced that the IBM Power4 is first the winner of its prestigious new Microprocessor Report Technology Award, honoring the most promising microprocessor technology disclosed in 1999.
		The winner was chosen by Microprocessor Report's staff of respected technology analysts and presented during MDR's Processing the Future 2000 industry forecast and award dinner.
		After nearly five years of hiding its activities from public scrutiny, Transmeta has finally opened its kimono, revealing what it claims is a revolutionary approach to x86 CPU design--the "chip" is half hardware and half software.
	www.mdronline.com /publications/mpw/issues/mpw034.html (544 words)

	IGM: IBM's Power4: Not in our future?
		XLR8YourMac is carrying a reader report that states rather emphatically that IBM's Power4 processors won't be used in future PowerMacs.
		I attended a briefing today on IBM's high performance computing technology, which is hinged on their Power4 CPU (this CPU has awesome performance in the various real-world benchmarks I have seen).
		After the briefing, I asked the presenter (a chief engineering manager from IBM) about the Power4 derivative for desktops and low end servers to be announced in October.
	www.insanely-great.com /news.php?id=908 (613 words)

	IBM to release cheaper Power4 servers - Hardware - News - ZDNet Asia
		As a result, the smallest Power4 server, the p670, contains four chips and starts at US$178,000, while the next smallest is an eight-processor box that contains two modules.
		Along with the new package for the Power4, IBM will be able to adjust the configurations of the new server by varying the internal configuration of the Power4 chip.
		From a silicon point of view, the new version of the Power4 is identical to its predecessor, sources said.
	www.zdnetasia.com /news/hardware/0,39042972,39049461,00.htm (693 words)

	The 64-bit saga POWER4 vs Itanium2 (Site not responding. Last check: 2007-10-12)
		For the next few days still, the 1.3 GHz POWER4 is the champion 64-bit CPU on both integer and FP portions of the SPEC2000 benchmark suite.
		Internally, even though the instruction set structure may not be as elegant as Alpha's, POWER4 is close enough - in fact, its design philosophy bears the most resemblance to the dying performance leader.
		As it sheds the remaining baggage that blocks fast speed ramps and moves towards the mainstream (Apple?), this architecture could be well positioned for the final 64-bit showdown.
	www.theinquirer.net /Default.aspx?article=4266 (1966 words)

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