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Topic: POWER5

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	IBM plots new Unix server chips \| CNET News.com
		Power5 will be able to take over software tasks commonly used in the operating system such as packaging data to be sent to networks, said Ravi Arimilli, an IBM Fellow and the chief technology officer for the Power line of chips.
		The Power5 and Power6 processors, to be detailed at IBM's analyst conference in Palisades, N.Y. and expected to arrive in 2004 and 2006, are the successors to the highly regarded Power4 chip at the heart of the p690 "Regatta" Unix servers.
		Power5, which will be built initially with 130-nanometer (0.13 micron) features, also will feature "simultaneous multithreading," a feature that allows a single chip to act as two.
	news.com.com /2100-1001-892774.html (1905 words)

	IBM JRD 49-4/5 \| POWER5 system microarchitecture (Site not responding. Last check: 2007-11-01)
		In POWER5 systems, by moving the L3 cache from the memory side of the fabric to the processor side of the fabric, we are able to more frequently satisfy L2 misses with hits in the 36-MB off-chip L3, thus eliminating L3 hit traffic from the interchip buses.
		In POWER5 systems, the size of the issue queues remains the same as in POWER4 systems, with the exception of the floating-point issue queues, which were increased from a total of 20 entries to 24.
		POWER5 chips on the MCM are interconnected with two buses in a ring configuration, with data flowing in opposite directions on the two buses.
	researchweb.watson.ibm.com /journal/rd/494/sinharoy.html (8478 words)

	IBM JRD 49-4/5 \| Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems (Site not responding. Last check: 2007-11-01)
		While the POWER5 design point maintains both binary and structural compatibility with the POWER4 design, allowing existing executable files to continue to execute properly and application optimizations to advance, enhanced performance and functionality was introduced in the POWER5 processor and system design.
		The POWER5 DPM design approach relied on dynamically gating the functional clocks to logical subsections of the design that were not currently being used by the executing instruction streams.
		However, the POWER5 team identified approximately 95% of all design problems prior to the release of the chip to manufacturing, and less than 1% of the problems would have a serious impact on the bring-up of hardware in the laboratory.
	researchweb.watson.ibm.com /journal/rd/494/victor.html (7946 words)

	[No title]
		POWER5 is an evolutionary advance over POWER4, retaining many of the same characteristics and adding some new features into the mix.
		The Power5 doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.
		The POWER5 can dynamically, under software control, assign each thread what we might call "priority points" from a eight-point "priority pool." So thread zero might have a score of 6, meaning that thread one would have a score of 2.
	arstechnica.com /articles/paedia/cpu/mpf-2003.ars (1084 words)

	Macworld: News: IBM's Power5 worth a second look
		First introduced last summer, the Power5 is a one-two punch, a triumph of engineering from a company that excels not only in processor design but also in the submicron science of chip manufacturing and packaging.
		The Power5 also foreshadows a new generation of 64-bit, PowerPC-based workstations and servers from IBM's longtime partner in Power, Apple Computer Inc. And IBM recently pulled an unexpected move for a company built on patents by publishing the Power architecture and tools under an open license.
		Finally, Power5 uses what it knows about the facilities needed by each RISC instruction to, in essence, power down portions of the chip that aren't needed at that moment.
	www.macworld.com /news/2004/12/22/power5/index.php (1904 words)

	IBM's POWER5: The multi-chipped Monster (MCM) revealed
		POWER5 tries to address many such situations where a bundle execution couldn't proceed because of some resource conflict or dependency.
		L3 cache on POWER5 is on the MCM now, and so its bus now operates at half CPU speed, rather than one third of CPU speed like on POWER4.
		So, expect a 64-way POWER5 "Squadron" follow-on to the current p690 POWER4+ "Regatta" to be the very first system sometime, maybe the middle of next year, using this approach.
	www.theinquirer.net /?article=12217 (1023 words)

	[No title]
		IBM's POWER5 servers are currently the reigning champs in many of the benchmarks that the industry uses to assess high-end mainframe servers, and even though most of us will never get our hands on a POWER5 the system's stellar scores have generated plenty of excitement in the hardware enthusiast community.
		The first way that POWER5 ensures reliability is by providing some redundancy at the system level (i.e., multiple Ethernet controllers, etc.).
		Pattnaik said that if IBM were to publish the detailed monitoring information for end users to access, then the company would feel obliged to maintain backwards compatibility in future iterations, and so they'd be limited in the changes they could make to the scheme.
	arstechnica.com /articles/paedia/cpu/POWER5.ars (1000 words)

	First IBM Power5 server to debut Monday \| CNET News.com
		IBM's Power5 chip is a 64-bit processor that competes with high-end chips from Intel, Sun Microsystems and Hewlett-Packard.
		Power5 has better partition abilities than Power4, with each chip able to run as many as 10 separate operating systems instead of just one.
		And Power5 is the foundation not just of the i5 and p5 lines but also of a new top-end storage system, IBM executives have said.
	news.com.com /2100-1010_3-5203401.html (1703 words)

	The Four Hundred--p5 Power5+ Machines Preview Possible Future i5s
		This version of the Power5+ chip is smaller and cooler, which means IBM can crank the clock speed up a little bit; the exact wattages and relative performance figures for the 1.9 GHz Power5+ compared to the 1.65 GHz Power5 chip were not available at press time.
		The new--and somewhat unexpected--addition to the Power chip family with the Power5+ launch is a new Quad Core Module (QCM), which puts four Power5+ cores running at a slower 1.5 GHz on a single piece of ceramic and plugging into a single "Squadron" server socket on the motherboards where IBM is initially supporting it.
		Moving to the new 1.9 GHz Power5+ DCM makes no sense in a single-core machine, since heat is not much of an issue and the Power5+ needs to be conserved for machines with at least two cores activated.
	www.itjungle.com /tfh/tfh101005-story03.html (2777 words)

	IBM ships record-breaking new POWER5+ servers Enterprise Networks & Servers - Find Articles
		The new IBM System p5 Express servers are equipped with POWER5+ microprocessor technology and are specifically designed for the processing requirements of SMB companies or branch locations running business-critical database applications in retail, wholesale, distribution and financial services.
		POWER5+ is a "server on a chip" containing two processors, a high-bandwidth system switch, a large memory cache and I/O interface.
		With the POWER5+ processor, IBM is enhancing the features and speed that have made the POWER5 processor the measuring stick of UNIX servers, while offering customers the price performance value they need to justify a long-term investment in their data centers
	www.findarticles.com /p/articles/mi_qa4137/is_200510/ai_n15742437 (830 words)

	MacSlash \| IBM Announces Power5+ Processors
		Today IBM announced new Power5+ processors for their UNIX servers, featuring multi-core processors that pack more processing power onto each module: up to 16 cores in the high-end model.
		Considering that their top of the line model is already a 32-way Power5 system, putting in 8-core Power5+'s would just be insane.
		The IBM Power5 is a whole new line of chips - and currently has nothing at all to do with the chips Apple uses called G5s.
	macslash.org /article.pl?sid=05/10/04/1313249 (807 words)

	Macworld: News: Microprocessor Forum: IBM talks Power5
		The Power5 is intended to build upon the Power4 design with enhancements made to improve performance, allow more processors to be used in a system and to improve power efficiency.
		The Power4 and Power5 both have an off-chip L3 cache, but IBM designed the L3 cache to connect directly to the L2 cache instead of between the memory controller and the processor like on the Power4.
		Sinharoy said that the Power5 is working in IBM's labs now and is on schedule to ship next year; however, he made no mention of benchmark performance or clock speed of the new processor.
	www.macworld.com /news/2003/10/14/power5 (897 words)

	IBM POWER5 (Site not responding. Last check: 2007-11-01)
		As remarked in section IBM POWER4+ the POWER5 chip will replace the POWER4+ in the near future and we therefore present some features of this chip here.
		Because of the higher density on the chip (the POWER5 is built in 130 nm technology instead of 180 nm used for the POWER4+) more devices could be placed on the chip and they could also be enlarged.
		There is another feature of the POWER5 that does not help for regular data access but which can be of benefit for programs where the data access is not so regular: Simultaneous Multithreading (SMT).
	www.phys.uu.nl /~steen/web04/power5.html (557 words)

	IBM Press room - 2004-05-03 IBM Unleashes eServer i5 Systems with POWER5 - United States
		Powered by POWER5 microprocessors, the most powerful 64-bit chips ever built by IBM, the IBM eServer i5 can integrate and run multiple operating systems simultaneously including i5/OS, Windows, Linux and AIX 5L.
		POWER5 features an impressive 276 million transistors per processor, and is manufactured with IBM's 0.13-micron copper wiring and SOI (Silicon-on-Insulator) technologies.
		Since the POWER5 chip has two processor cores, SMT essentially allows the chip to run four application threads at the same time, thereby reducing the time it requires to complete a task.
	www-03.ibm.com /press/us/en/pressrelease/7067.wss (1145 words)

	X-bit labs - Hardware news - IBM’s POWER5 Chip with 8 Cores and 144MB Cache Showcased.
		As revealed earlier this year, the POWER5 is healthy going from tape-out to mass production in 2004, now you can see the proof here.
		POWER5 typical processor is a 95mm x 95mm MCM with 4 chips (each chip contains 2 cores) feature astonishing 144MB of cache memory.
		POWER5 feature on chip memory controller that can address up to 1024GB of RAM.
	www.xbitlabs.com /news/cpu/display/20031017104313.html (346 words)

	IBM attacks Unix rivals with Power5 \| Tech News on ZDNet
		IBM has a simple future planned for the Power line: Power5 this year, a faster remake called Power5+ in 2005, Power6 in 2006, Power6+ in 2007, Power7 in 2008 and Power7+ in 2009, said Arimilli, who has just been named chief architect of the Power7 models.
		Also coming with Power5 is simultaneous multithreading (SMT), an ability for a single processor to handle some of the work of two.
		One of the major new features of the Power5 servers is "micro-partitioning," the ability to run as many as 10 operating systems on each processor.
	news.zdnet.com /2100-9584_22-5266768.html (1720 words)

	EETimes.com - IBM weaves multithreading into Power5
		With Power5 it appears to the operating system that there are four CPUs on each chip," said Mark Papermaster, director of microprocessor design for IBM's server division.
		With the Power5, it now hopes to be the first to blend both multi-core and multithreading technologies.
		The Power5 sports a new CPU core with execution units redesigned for multithreading.
	www.eetimes.com /news/semi/showArticle.jhtml?articleID=10800757 (947 words)

	IBM Power5 will be multicore and multithread
		The Power5 64bit processor is still dual core but adds multithreading capabilities to both cores, according to Silicon Strategies.
		The Power5 will appear to the operating system as four processors, despite being a single chip.
		IBM has said that the Power5 prototypes are already meeting expectations.
	www.theinquirer.net /?article=7973 (254 words)

	Ravi Arimilli, IBM Fellow and Chief Architect
		On Power5, we really had time to use more technologies and sit back and talk to, for example, the CIO from American Express, the CIO from State Farm, the CIO from Home Depot.
		Q: For Power5, you and your team came up with a lot of features you are clearly proud of, including the micro-partitioning virtualization.
		The model we have right now is what I call "real-time design changes into a roadmap of chips." We have a Power5+ in a laboratory running to be announced next year.
	www.internetnews.com /ent-news/article.php/3385241 (1648 words)

	IBM prepares second phase of Power5 - ZDNet UK News
		Like the existing Power4 models, Power5 includes two processing units on each slice of silicon, a design called "dual-core." However, each Power5 core can run two separate sequences of instructions, called "threads," making each slice of silicon function somewhat like four conventional processors.
		The Power5 processors are expected to be offered at speeds of 1.5GHz, 1.65GHz and 1.9GHz, sources familiar with the products said.
		One major improvement in partitioning from Power4 to Power5 is better "virtualisation," an abstraction technique that lets multiple partitions share the same network and storage adapters.
	news.zdnet.co.uk /hardware/servers/0,39020363,39159579,00.htm (711 words)

	IBM pumps Unix line full of Power5+ \| The Register
		The company today kicked off the release of the Power5+ chip by announcing three new systems that slot into the low-end of its Unix server line, a new workstation and a server aimed at researchers.
		The lower-end servers coupled with a surprisingly slow introductory Power5+ speed may bother some customers who were looking for IBM to really flex its computing muscle in the near-term.
		This means the Power5+ has a smaller size than the regular Power5 and is more energy efficient.
	www.theregister.co.uk /2005/10/04/ibm_power_plus (950 words)

	PRESS RELEASE IBM Introduces New Low-Priced POWER5 Server Based on Linux (Site not responding. Last check: 2007-11-01)
		The introduction of the IBM eServer™ OpenPower™ 710 marks IBM's continued commitment to extend POWER5 performance for Linux environments to companies of all sizes.
		The 2-way 1.6 GHz POWER5 IBM eServer p5 520 result running 2 threads per processor is 5,287.
		IBM, the IBM logo, BladeCenter, eServer, Micro-Partitioning, OpenPower, POWER, Power Architecture, POWER5 and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in the United States or other countries or both.
	www.marketwire.com /mw/release_html_b1?release_id=79508 (1562 words)

	IBM Brings Power5+ to iSeries Servers (Site not responding. Last check: 2007-11-01)
		IBM, of Armonk, N.Y., first introduced the Power5+ chip in October in the System p5 family of servers, a move that also included the melding of the pSeries with the OpenPower servers designed specifically for Linux.
		Power5+ runs at speeds of up to 2.2GHz and offers the i5 servers up to a 33 percent increase in performance over the current Power5-based iSeries systems.
		The Power5+ processor will be available on all i5 systems—the 520, 550, 570 and 595—Feb. 14.
	www.eweek.com /article2/0,1895,1917221,00.asp (1129 words)

	CoSORT
		IBM eServer i5 and eServer p5 systems are an advanced line of servers that can run Linux on POWER5 microprocessors while leveraging Micro-Partitioning™, an IBM Virtualization Engine™ technology, to achieve unprecedented computing performance and reduced costs for a wide range of business and scientific applications.
		Prior to porting CoSORT V8 to POWER5, IRI ported CoSORT to IBM eServer iSeries platforms under both LINUX and OS/400 PASE.
		CoSORT's sort benchmark of 711MB in 22 seconds on both machines "should be indicative of the new level of price-performance CoSORT users can expect when transforming their operational data into information," Friedland observed.
	www.cosort.com /public/news/pr/power5.htm (565 words)

	IBM Unveils New Power5 Unix Servers - News by InformationWeek
		IBM's debuting four systems incorporating its Power5 microprocessor that mark a major refresh of its Unix server lineup.
		Later this year, IBM plans to introduce the Power5 chip in other computing lines, including blade servers.
		The 64-bit, Power5 chip made a limited debut earlier this year in IBM's iSeries servers.
	www.informationweek.com /story/showArticle.jhtml?articleID=23900519 (471 words)

	IBM: Power5 Chip to Tap Threading
		Since Armonk, N.Y.-based IBM's Power4 implemented two processor cores per chip, the Power5 will present four virtual cores to the operating system—two physical cores and two virtual ones—said Ron Kalla, a system designer for IBM, in a Wednesday presentation at the Hot Chips conference here.
		Kalla characterized the Power5 as an extension to the Power4 architecture, with additions tacked on to support the additional thread.
		IBM architected the Power5 to allow the operating system to turn the Power5's SMT capabilities on and off to maximize performance, Kalla said.
	www.extremetech.com /article2/0,3973,1226834,00.asp (793 words)

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