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Topic: PRAM consistency

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	PRAM consistency - Wikipedia, the free encyclopedia
		PRAM consistency (pipelined random access memory) also known as FIFO consistency
		All processes see memory writes from one process in the order they were issued from the process.
		Only the write order needs to be consistent, thus the name pipelined.
	en.wikipedia.org /wiki/PRAM_consistency (86 words)

	Consistency model - Wikipedia, the free encyclopedia
		In computer science, in a distributed system such as a distributed shared memory system or a distributed data store such as a database, filesystem, or web caching system, there are a number of possible data consistency models.
		The data consistency model specifies a contract between programmer and system, wherein the system guarantees that if the programmer follows the rules, memory will be consistent and the results of memory operations will be predictable.
		This page was last modified 12:19, 28 July 2006.
	en.wikipedia.org /wiki/Consistency_model (117 words)

	[No title] (Site not responding. Last check: 2007-10-23)
		PRAM stands for pipelined RAM, becuase writes by a single process can be pipelined, that is, the process does not have to stall waiting for each one to complete before starting the next one.
		PRAM consistency is contrasted with causal consistency in the following figure.
		The sequence of events shown here is allowed in PRAM consistent memory but not with any of the stronger models we have seen so far.
	www.cs.nmsu.edu /~kkottapa/cs573/pram.html (162 words)

	[No title]
		Consistency models (5) (a) The figure below shows a sequence that is allowed with causally consistent memory, but not with sequentially consistent memory.
		State what it is that causes the sequence of events to meet causal consistency requirements but not sequential consistency requirements and why this is so using the definitions of sequential and causal consistency.
		State what it is that causes the sequence of events to meet PRAM consistency requirements but not causal consistency requirements and why this is so using the definitions of PRAM and causal consistency.
	www.eas.asu.edu /~cse536/old_exams/fe_sp99.doc (638 words)

	Distributed Shared Memory (Site not responding. Last check: 2007-10-23)
		The pipelined RAM (PRAM) consistency model states that all writes done by a single process are received by all other processes in the order in which they were issued.
		Release consistency [Charochorloo, 1990] alleviates this problem by splitting the synchronization variable into two parts: acquire access is requested on entry to a critical section (no propagation of local changes is made) and release access is requested after the critical section completes (no updates are performed, only local changes are propagated).
		In using barriers with release consistency, an arrival at a barrier is a release and a departure from a barrier is an acquire.
	www.cs.rutgers.edu /~pxk/rutgers/syllabus/dsm.html (1476 words)

	The Jakarta Post - The Journal of Indonesia Today
		Pram, the abbreviated name by which he is usually referred to, is himself like a thick book, containing all sorts of stories.
		There is a great consistency in Pram's criticism, starting from his highly personal statements -- about his relationship with his family for example, to his statements about language, politics and history -- aspects that occupy important places in his body of work.
		Pram's complaint is not simply one of a disgruntled grandfather who hates to see his grandchildren glued to trashy TV.
	www.thejakartapost.com /yesterdaydetail.asp?fileid=20060226.N01 (1134 words)

	CS 551: Consistency & Replication, Types of Consistency
		A shared-memory system is said to support the strict consistency model if the value returned by a read operation on a memory address is always the same as the value written by the most recent write operation to that address, irrespective of the locations of the processes performing the read and write operations.
		Unlike the sequential consistency model, in the causal consistency model, all processes see only those memory reference operations in the same (correct) order that are potentially causally related.
		FIFO Consistency Model: For FIFO consistency, "Writes done by a single process are seen by all other processes in the order in which they were issued, but writes from different processes may be seen in a different order by different processes.
	www.cs.colostate.edu /~cs551/CourseNotes/Consistency/TypesConsistency.html (710 words)

	DSM Implementation Related Issues
		The causal consistency model represents a weakening of sequential consistency in that it makes a distinction between events that are potentially causally related and those that are not.
		PRAM stands for Pipelined RAM, because writes by a single process can be pipelined, that is, the process does not have to stall waiting for each one to complete before starting the next one.
		Although PRAM consistency and processor consistency can give better performance than the stronger models, they are still unnecessarily restrictive for many applications because they require that writes originating in a single process be seen everywhere in order.
	www.niksula.cs.hut.fi /projects/ohtdsm/documents/kirjtutk/cmodels.html (5875 words)

	Pram MP3 Downloads - Pram Music Downloads - Pram Music Videos (Site not responding. Last check: 2007-10-23)
		This mix of consistency and unpredictability continues on Dark Island, an album whose sound and artwork suggests a carnival at midnight or a...
		Disconcerting and maze-like, Pram's second full-length effort shapes and refines the ideas of their previous records; Helium's primary components -- Moog burblings, exotic rhythms and cool-toned horns -- are more typically the building blocks of lounge music, but Pram is instead all about uneasy listening, cutting and pasting schizophrenic sound...
		Pram's minimalist, Krautrock-influenced brand of electronica is not for everyone (singer/lyricist Rosie Cuckston's little-girl voice seems to be the deal-breaker for many), but their fifth release, 1995's Sargasso Sea, is a good entry point for the dubious.
	www.mp3.com /pram/artists/119678/discography.html (419 words)

	Practical PRAM Programming - Errata (Site not responding. Last check: 2007-10-23)
		In contrast, sequential consistency requires consistency only for the memory accesses in that it implies some linear order of all memory accesses by all processors such that the effect of a write access, once applied to the memory, becomes visible to all processors immediately.
		An imaginary global observer of a sequentially consistent system may see that pending reads could return the old value after the write was committed to the memory, but in that case the read was "overtaken" by the write and thus comes before the write in the linear order of memory accesses.
		Hence, sequential consistency is nondeterministic and not programmable.
	www.ida.liu.se /~chrke/ppp/errlist.html (497 words)

	Citations: The Power of Processor Consistency - Ahamad, Bazzi, John, Kohli, Neiger (ResearchIndex) (Site not responding. Last check: 2007-10-23)
		A history H is sequentially consistent if there is a legal linear sequence SC Gamma of the set of operations on H such that: i) 8o1; o2 where o1 po Gamma o2 then o1 SC Gamma o2.
		We consider two varieties of processor consistency, called PCG and PCD in [2] The authors use this terminology to distinguish the version used in the DASH shared memory computer (PCD) from the definition....
		Sequential Consistency: A history is sequentially consistent if there is a legal linear sequence of that respects the order SC which is defined as follows: i) o 1, o 2 : if o 1 po o 2 then o 1 SC o 2.
	citeseer.ist.psu.edu /context/64636/341070 (2917 words)

	Application Specific Data Replication for Edge Services (Site not responding. Last check: 2007-10-23)
		Although strong consistency and high availability are difficult to achieve for a large-scale system using a generic database interface for data replication, the semantics of the specific shared objects needed by the distributed bookstore are relatively straightforward.
		Also note that although FIFO consistency provides strong guarantees on the order that updates are observed, it does allow time delays between when an update occurs and when it is seen by an edge server.
		It is worth noting that the small back-order rate shown in Figure 6 only represents the system consistency in the extreme cases where inventory is small and low, 2-6 copies per book with 5 different books, and the workload is unbalanced.
	www.cs.utexas.edu /users/lgao/lead (10862 words)

	[No title]
		So, release consistency is introduced.¡HE'E'ó¨Release Consistency¡ ÿÿþ¨"Three classes of variables: Ordinary variables Shared data variables Synchronization variables: Acquire and Release (CS) DSM has to guarantee the consistency of the shared data variables.
		On acquire, the memory makes sure that all the local copies of protected variables are made consistent and changes are propagated to other machines on release.
		The acquire and release accesses must be processor consistent (sequential consistency is not required).¡ggó ¨%Implementation of Release Consistency¡&& ÿÿþ¨ Two types of implementation: Eager release consistency: Broadcast of modified data to all other processors is done at the time of release.
	www.cis.ksu.edu /~sathish/Presentation.ppt (686 words)

	Memory Consistency Models
		The intuitive notion of memory consistency is the strict consistency model.
		The last scenario in the sequential consistency section, which wasn't valid for sequential consistency, would be valid for processor consistency.
		One final note on processor consistency and pram consistency is that some authors make processor consistency slightly stronger than PRAM by requiring PC to be both PRAM consistent and cache coherent.
	www.cs.nmsu.edu /~pfeiffer/classes/573/notes/consistency.html (2856 words)

	Underdog Group - Chapter 9
		Consistency: A transaction must begin in a consistent state and leave the sysem in a consistent state.
		PRAM Consistency Model: "Only write operations performed by a single process are required to be viewed by other processes in the order that they were performed."
		Which would ensure consistency depending upon its ability to distinguish between a node crash and delayed response when it comes to asynchronous communication between the object servers and the clients.
	shrike.depaul.edu /~hdesai1/420/final/000_starthere.html (2413 words)

	Distributed Shared Memory
		Implementing causal consistency effectively means keeping a dependence graph of what operations are dependent on what other operations.
		Idea: Release consistency, plus associations between ordinary shared variables and locks or barriers: Acquires and releases are specific to specific synchronization variables.
		Sequential consistency is feasible but has poor performance.) On the other hand, more relaxed consistency models improve performance by reducing the volume of writes-to-memory, but application programming is more complex.
	www.rscc.cc.tn.us /faculty/bell/etsu/OpSys/t6.html (3963 words)

	COMP 413: Lecture 7
		With release consistency, all local updates are propagated to other processors during release of shared variable.
		With entry consistency, each shared variable is associated with a synchronization variable.
		Observation: If we discard whether all data is globally consistent (as is the case with release consistency), or specific data is consistent (entry consistency), we need to distinguish three access methods.
	www.cs.rice.edu /~druschel/comp413/lectures/replication.html (1710 words)

	Citebase - A Unified Theory of Shared Memory Consistency (Site not responding. Last check: 2007-10-23)
		Authors: Steinke, Robert C. Nutt, Gary J. Memory consistency models have been developed to specify what values may be returned by a read given that, in a distributed system, memory operations may only be partially ordered.
		Before this work, consistency models were defined independently.
		Every consistency model previously described in the literature can be defined based on our four properties.
	www.citebase.org /cgi-bin/citations?id=oai:arXiv.org:cs/0208027 (180 words)

	Talks in 2000 (Site not responding. Last check: 2007-10-23)
		In the second part of the talk, I will discuss a combined theoretical and practical view on specifying and implementing consistency conditions for such a service.
		This includes a formal definition of a set of basic consistency conditions which are given in a very abstract, implementation independent manner.
		I will show that common consistency conditions such as sequential consistency, causal consistency, and PRAM can be formally specified as a combination of these more basic conditions.
	www.ifi.uni-klu.ac.at /Colloquia/2000/1003Friedman (286 words)

	Fork
		The PRAM (Parallel Random Access Machine) is a strictly synchronous MIMD multiprocessor with a sequentially consistent shared memory that can be accessed in unit time.
		Hence, a simple parallel programming model (and the PRAM is the simplest one) could be a realistic option for a future general-purpose programming model.
		New textbook on PRAM theory and practice, emulation techniques, SB-PRAM architecture, Fork language description, Fork compilation, parallel algorithmic paradigms and programming techniques, the PAD library of PRAM algorithms and data structures, and the implementation of FView, a larger parallel application in Fork.
	www.ida.liu.se /~chrke/fork (2146 words)

	[No title]
		(Registers) Illustrate: -> directory-based weakly consistent write invalidate -> problem with race conditions: - polling on a shared variable - doing writes in a CS, but not the reads (!!!) ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- Topic: Release consistency Observation: logically, there is a difference between locking and unlocking (or, similarly, between entering and leaving a critical section).
		Acquire and release operations must be processor consistent (sequential consistency is not strictly required).
		An acquire requires you to wait for all remote changes before corresponding release(s) to be locally applied.
	www.cs.utah.edu /classes/cs7460/lectures/lecture11.txt (630 words)

	PRAM Consistency and Processor Consistency (Site not responding. Last check: 2007-10-23)
		In causal consistency, it is permitted that concurrent writes be seen in a different order on different machines, although causally related ones must be seen in the same order by all machines.
		The next step in relaxing memory is to drop the latter requirement.
		PRAM consistency is due to Lipton and Sandberg.
	cs.gmu.edu /cne/modules/dsm/orange/pram_con.html (139 words)

	[No title]
		If the contract is followed, results are predictable (to the limit of the contract).
		Before a realse is allowed to be perfromed, all previous reads and write done by the process must have completed.
		The acquire and realse accesses must be processor consistent (sequenctial consistency is not required).
	www.ndsu.nodak.edu /instruct/juell/cs475s00/foils/distributed-memory.html (803 words)

	[No title]
		Concurrent writes may be seen in a different order on different machines.¡.¼ 2¨ð- ðD ð0È~¿Àÿ ðZ Ò ðÍ¨Weakens sequential consistency by making distinction between events that are potentially causally related and events that are not.
		ßÍÿð0àÐp ð@¨èPRAM is a memory model in which writes performed by a single process are seen by all other processes in the order in which they were issued, but writes from different processes may be seen in different orders by different processes.¡
		Concurrent writes may be seen in a different order on different machines.¡2¼ 2Ì3þ¨ð+ ðD ð0È~¿Àÿ ð`P0 ðË¨Weakens sequential consistency by making distinction between events that are potentially causally related and events that are not.
	www.cs.technion.ac.il /~cs236370/lectures/L7ProcessorConsistency.ppt (492 words)

	Characterizations for Java Memory Behavior - Gontmakher, Schuster (ResearchIndex) (Site not responding. Last check: 2007-10-23)
		The work is based on the operational definition of the Java memory consistency as given in the Java Language Specification [6].
		We study the relation of Java memory behavior to that of some well known models, proving that Java is incomparable with PRAM Consistency and with both variants of Processor Consistency; it is neither stronger nor weaker.
		The JVM is powered by an interpreter loop; on each iteration the next bytecode is executed.
	citeseer.ist.psu.edu /316393.html (466 words)

	IBM Research \| Israel \| Seminars \| Java Consistency: Non-Operational Characterizations for the Java Memory Behavior
		The work is based on the operational definition of the Java memory consistency as given in the Java Language Specification.
		We first compare Java memory behavior to that of some previously studied models, proving that Java is incomparable to PRAM Consistency and to both versions of Processor Consistency; it is neither stronger nor weaker.
		We show that a programmer can rely on Coherence for regular variables, Sequential Consistency for volatile variables, and Release Consistency when locks are employed.
	domino.research.ibm.com /comm/wwwr_seminar.nsf/pages/sem_abstract_11.html (192 words)

	[No title]
		Causal Consistency preserve the order of related events.
		Each process keep track of owner-ship\ *cause a lot of traffic How to find the copies that need invalidation 1.
		Synchronization variable ¡-2ª,ºmó$¡ª ¨îOrdinary Variable not shaded local to process that own them shared data variables visible to multiple process Sequentially consistent Synchronization variable only accessible through system supplied operations.
	master.cpe.ku.ac.th /~g4265087/advos/dsm.ppt (918 words)

	[No title]
		Memory consistency model: a formal specification of how the memory system will appear to the program.
		--> often referred to as a "contract" between the programmer and the memory architecture --> direct analogy exists for replicated data/objects Memory consistency protocol: protocol used by the memory system to implement the "contract" defined by the consistency model.
		Most modern processors support some form of relaxed consistency model (!) ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- Topic: Discussion Consider the kinds of distributed applications/services out there: - distributed file system - distributed data base - chat rooms - streaming video/audio - mobile/disconnected operation - wide area gaming -...
	www.cs.utah.edu /classes/cs7460/lectures/lecture10.txt (1061 words)

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