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Topic: Parallel bus

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	High speed parallel bus and data transfer method - Patent 4570220
		The parallel bus structure as defined by claim 1, wherein said arbitration means includes arbitration code generation means for transmitting a digital code corresponding to a unique arbitration number for each agent on arbitration lines, each arbitration number denoting a relative priority for access to said parallel bus.
		The bus structure as defined by claim 8, wherein a primary processor of said requesting agent generates a message request and passes said request to said message control means of said requesting agent, which encapsulates said request for transmission on said parallel bus.
		Parallel bus 35 supports three types of bus cycles which are initiated upon the request of an agent, such as for example processing unit 25, the "arbitration" cycle, the "transfer" cycle and the "exception" cycle.
	www.freepatentsonline.com /4570220.html (9830 words)

	Computer bus - Wikipedia, the free encyclopedia
		Early computer buses were literally parallel electrical buses with multiple connections, but the term is now used for any physical arrangement that provides the same logical functionality as a parallel electrical bus.
		The former referred to bus systems that were designed to be used with internal devices, such as graphics cards, and the latter to buses designed to add external devices such as scanners.
		An internal bus connects all the internal components of a computer to the motherboard (and thus, the CPU and internal memory).
	en.wikipedia.org /wiki/Computer_bus (1979 words)

	Computer bus -- Facts, Info, and Encyclopedia article (Site not responding. Last check: 2007-11-03)
		Early computer buses were literally parallel (Click link for more info and facts about electrical bus) electrical buses with multiple connections, but the term is now used for any physical arrangement that provides the same logical functionality as a parallel electrical bus.
		The classic, simple way to prioritise interrupts or bus access was with a (Flower chain consisting of a string of daisies linked by their stems; worn by students on class day at some schools) daisy chain.
		The former referred to bus systems that were designed to be used with internal devices, such as graphics cards, and the latter to buses designed to add external devices such as (An electronic device that generates a digital representation of an image for data input to a computer) scanners.
	www.absoluteastronomy.com /encyclopedia/c/co/computer_bus.htm (2490 words)

	Using MTBF to Analyze Bus Reliability (Site not responding. Last check: 2007-11-03)
		Typically the bus bandwidth can be partitioned in a fashion where each module is assigned a portion of the bandwidth and writes and reads from the bus during its allocated time.
		In the star topology, each bus is an SSM as compared to the parallel bus where the bus is a CSM.
		The primary star bus is connected from each channel module to the primary NM while the secondary bus is connected from each channel module to the secondary or standby NM.
	www.commsdesign.com /printableArticle?articleID=22102999 (2905 words)

	ATA Bus Interface Description, Pin out and IDE PinOut and Signal Names
		The IDE bus is used in Personal Computers [PCs] as a hard-drive or peripheral bus to interconnect the PC mother board and a hard drive.
		The bus is source [series] terminated with a 33 ohm resistor.
		Keep in mind that the Parallel ATA [PATA] Bus is being replaced by the Serial ATA: [SATA] bus.
	www.interfacebus.com /Design_Connector_IDE.html (2213 words)

	Computer bus - Open Encyclopedia (Site not responding. Last check: 2007-11-03)
		As data rates increase, the problems of timing skew across parallel buses become more and more difficult to circumvent.
		Often, a serial bus can actually be operated at higher overall data rates than a parallel bus, despite having fewer electrical connections.
		S-100 bus or IEEE 696, used in the Altair and similar computers
	open-encyclopedia.com /Computer_bus (1900 words)

	Toolbox: Parallel Bus Revealed
		The parallel bus interface runs at the same speed as the 6502 microprocessor-and it can transfer information more than 40 times faster than the serial connector.
		WHAT THE PBI IS Basically, the parallel bus connector is an extension of the 6502 data, address, and control signals.
		The parallel device cannot use OS Floating Point routines because the device's ROM is mapped into those same locations.
	www.atarimagazines.com /v3n9/Parallel_Bus.html (1246 words)

	Philips Semiconductors - I2C Logic [Products - I2C/SMBus Bus Controllers and Bus Controller Functions]
		This is commonly referred to as the bus master.
		C bus is carried out on a byte-wise basis using interrupt or polled handshake and controls all of the I
		C ports to smart devices or to convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the PC board.
	www.standardics.philips.com /products/i2ccontrollers (515 words)

	ppbus(4) - Parallel Port Bus system
		The logical parallel port model chosen for the ppbus system is the PC’s parallel port model.
		The EPP protocol was originally developed as a means to provide a high performance parallel port link that would still be compatible with the standard parallel port.
		During attachment of the ppc driver, a new ppbus structure is allocated, then probe and attachment for this new bus node are called.
	www.gsp.com /cgi-bin/man.cgi?section=4&topic=ppbus (1459 words)

	PCI Description; Peripheral Component Interface for the PC, background info on the PCI Bus
		Flow control is added to allow the bus to operate with slower devices on the bus, allowing the bus to operate at their speed.
		The main physical difference between the two bus formats lay with the connectors, the main electrical difference is a differential serial bus instead of a single ended parallel bus.
		Keeping in mind that Parallel PCI will be around for years to come just as the ISA bus is still around.
	www.interfacebus.com /Design_Connector_PCI.html (1666 words)

	Circuit Cellar - Digital Library - CCO
		With several dozen ports connected in parallel, the sum of parasitic capacitance tends to slow the parallel bus down, lowering its bandwidth.
		An analysis of the required bandwidth of the bus, which depends on the estimated peak data flow on the bus and the actual bus bandwidth, must be performed before a design is finalized.
		Because separate parallel port address and data buses mean a higher pin count for a DSP package, and thus a larger package size, most DSP parallel ports have a multiplexed address and data bus parallel port.
	www.circuitcellar.com /library/ccofeature/arnold0300/c0300sa2.htm (1555 words)

	Serial ATA (Site not responding. Last check: 2007-11-03)
		The parallel ATA interface has been in use on desktop systems as the mainstream internal storage inter-connect, since the 1980's (over 15 years!).
		Physically and electrically, the current parallel bus has run into limitations that will prevent this bus from providing higher speeds of data transfers.
		Setting the goal to be compatible and at cost parity with current parallel ATA drives when in volume, the SerialATA organization is promoting the adoption of Serial ATA in all systems where ATA drives are being used today.
	www.bellmicro.com /vendorshowcase/newseagate/SerialATA.asp (810 words)

	myatari.net : The Atari XL Parallel Bus Interface Part I (Site not responding. Last check: 2007-11-03)
		As the term "parallel bus" suggests, the data are not tranferred serial, bit by bit, but parallel, which means 8 bits at a time.
		This is not even done at the pace of 19,200 baud, as the serial bus does, but at the maximum pace of the 6502 CPU.
		Every time data are transferred over the data bus, the CPU signals with these wires which storage location is meant to transmit or receive data.
	www.geocities.com /dr_seppel/pbi1_eng.htm (1047 words)

	Expanding the SCSI bus
		The parallel SCSI interface has increased in speed while using the same physical transmission mediums defined when the bus was more than 10 times slower.
		Parallel SCSI Expanders used as extenders separate a SCSI bus (SCSI domain) into more than one physical segment, each of which can have the full SCSI cable length for that type.
		All signal lines for the wide segment are terminated at the expander eliminating the potential hazards of improper terminations for the wide bus and simplifying the cabling for the narrow segment.
	www.shiloff.org /scsi (1603 words)

	Toolbox: Parallel Bus Revealed: Part 2 (Site not responding. Last check: 2007-11-03)
		The decode logic selects the device when the assigned PBI addresses are presented on the address bus.
		When the computer wants to talk to a parallel bus peripheral, it enables the decode logic with a signal called External Enable.
		The decode logic decides whether the address on the bus is for the device or for the 2K ROM.
	www.atarimagazines.com /v3n10/parallelbus.html (786 words)

	IEEE 488 Computer Encyclopedia Enterprise Resource Directory Complete Guide to Internet (Site not responding. Last check: 2007-11-03)
		It allows up to 15 intelligent devices to share a single bus, with the slowest device participating in the control and data transfer handshakes to drive the speed of the transaction.
		To paraphrase from the HP 1989 Test & Measurement Catalog (the 50th Anniversary version): The HP-IB has a party-line structure wherein all devices on the bus are connected in parallel.
		The 16 signal lines within the passive interconnecting HP-IB (IEEE-488) cable are grouped into three clusters according to their functions (Data Bus, Data Byte Transfer Control Bus, General Interface Management Bus).
	www.jaysir.com /computer-encyclopedia/i/ieee-488-computer-terms.htm (223 words)

	Parallel Bus Interface
		PIN 35 is the IRQ (Interrupt Request) input from the Parallel Bus Interface devices.
		PIN 34 is the Reset (POR) output to the Parallel Bus Interface devices.
		The ROM containing this code is physically located in a Parallel Bus Adapter.
	www.atarimuseum.com /articles/pbi-1.html (1332 words)

	The educational encyclopedia, I2C bus, I2S bus (Site not responding. Last check: 2007-11-03)
		C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other.
		I2C bus protocol the I2C bus physically consists of 2 active wires and a ground connection.
		I2C FAQ the BUS physically consists of 2 active wires and a ground connection.
	users.pandora.be /educypedia/electronics/I2C.htm (326 words)

	FreeBSD parallel port bus framework (Site not responding. Last check: 2007-11-03)
		Parallel port chipset support is provided by ppc(4).
		Some parallel port chipsets are explicitly supported by ppc: detection and initialization code has been written according to specs datasheets.
		e.g what a process writes to the parallel port may be read on the remote host parallel port if they're connected with cable given in ppi.c.
	people.freebsd.org /~nsouch/ppbus.html (494 words)

	Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to ...
		Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to receiving units when ready (US5548785)
		Interface for logic simulation using parallel bus for concurrent transfers and having fifo buffers for sending data to receiving units when ready
		Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information
	www.delphion.com /details?pn=US05548785__ (504 words)

	MT9085B - 1024 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (PAC) (Zarlink Semiconductor)
		The MT9085 Parallel Access Circuit (PAC) provides an interface between an 8 bit, parallel time division multiplexed bus and a serial time division multiplexed bus.
		A single PAC device will accept data clocked out on the parallel bus of the MT9080 (SMX) and output it on 32/16 time division multiplexed serial bus streams.
		A second device can be configured to perform the conversion from the serial format into an SMX compatible parallel format.
	products.zarlink.com /product_profiles/MT9085B.htm (340 words)

	Rambus announces parallel bus logic interface (Site not responding. Last check: 2007-11-03)
		Rambus Inc, a leading developer of chip-to-chip interface products and services, recently introduced its parallel bus logic interface family, code-named Redwood.
		The Redwood parallel bus interface family addresses intra-board applications including processor, chipset and network chip connections.
		It is optimized for low latency and low power parallel bus applications.
	www.dqchannelsindia.com /content/global/103030402.asp (164 words)

	MyAtari magazine : The Atari XL Parallel Bus Interface - Part 2 (Site not responding. Last check: 2007-11-03)
		For the TTLs directly connected to the CPU bus, we have to take care not to exceed the maximum fan-out of one standard TTL at each PBI pin.
		Input D1 of the flip-flop is connected to one bit of the data bus.
		Through a tri-state buffer (74126) the output of the flip-flop is connected to the CPU data bus.
	www.geocities.com /dr_seppel/pbi2_eng.htm (1522 words)

	EETimes.com - Rambus touts Redwood parallel bus (Site not responding. Last check: 2007-11-03)
		Redwood is differential physical-layer technology for running parallel chip-to-chip connections up to 6.4 GHz over 15 inches of a four-layer pc board.
		Designers have started discussions on HyperTransport 2, a backward-compatible version of the parallel bus that would take it to data rates in the range of Redwood.
		But he did say the development shows parallel buses will coexist with serial links for years because parallel interconnects offer advantages in latency, cost and die size.
	www.eetimes.com /story/OEG20030215S0010 (643 words)

	MT8920B - 32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (Zarlink Semiconductor)
		The ST-BUS Parallel Access Circuit (STPA) provides a simple interface between ST-BUS and parallel system environments.
		Parallel bus controller (mode 3) - no external controller required
		Product Lead-Times when quoted are not guaranteed and are provided as a general guideline only; they may be varied from time to time without notice.
	products.zarlink.com /product_profiles/MT8920B.htm (226 words)

	Rambus intros Redwood parallel bus system
		MEMORY IP COMPANY put a form to a set of parallel bus logic interfaces under the codename Redwood.
		The bus is used to connect different parts of a PC's circuitry, as this diagram shows.
		Redwood connects the CPU to the north bridge, and to the south bridge, while other Rambus tech such as RaSer and "Yellowstone" connect other different parts of the circuitry.
	www.theinquirer.net /Default.aspx?article=7846 (274 words)

	STD Bus Legacy Parallel I/O Card - LPM/MCM-PIO
		It is a highly versatile, 32 line parallel input/output controller designed to provide a variety of methods of I/O between a processor and peripherals.
		The card uses two Z80-PIOs which are software programmable and have four operating modes: Byte Input, Byte Output, Bi-directional and Bit Input/Output.
		A MCM/LPM prefix indicates the card has the same features and functionality and is available in both CMOS and regular NMOS/TTL logic.
	www.stdbus.com /products/std/lpmpio.html (251 words)

	Category - Parallel PCI-bus cards
		Cables (Ethernet, Firewire, Parallel, PS/2, Serial, USB and VGA)
		4 serial port, 1 parallel port PCI-bus card with 9-pin serial spider cable.
		4 serial port, 1 parallel port PCI-bus card with 25-pin serial spider cable.
	byterunner.com /byterunner/category=Parallel+PCI-bus+cards/... (167 words)

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