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Topic: Phase-locked loop


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In the News (Mon 19 Aug 19)

  
 Phase-locked loop - Wikipedia, the free encyclopedia
Phase noise is another type of jitter observed in PLLs, and is mostly caused by the amplifier elements used in the circuit.
Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated.
The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.
en.wikipedia.org /wiki/Phase-locked_loop   (2911 words)

  
 phase-locked loop - a Whatis.com definition - see also: PLL, phase-lock loop
A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven oscillator that is constantly adjusted to match in phase (and thus lock on) the frequency of an input signal.
PLLs are frequently used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM).
Since a PLL requires a certain amount of time to lock on the frequency of an incoming signal, the intelligence on the signal (voice, video, or data) can be obtained directly from the waveform of the measured error voltage, which will reflect exactly the modulated information on the signal.
searchnetworking.techtarget.com /sDefinition/0,,sid7_gci783790,00.html   (392 words)

  
 Phase-Locked Loop Tutorial, PLL
The loop may be broken between the VCO and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication.
Loop gain may be reduced by connecting a resistor between Pin 6 and Pin 7; this reduces the load impedance on the output amplifier and hence the loop gain.
The phase detector is a device that compares two input frequencies, generating an output that is a measure of their phase difference (if, for example, they differ in frequency, it gives a periodic output at the difference frequency).
www.uoguelph.ca /~antoon/gadgets/pll/pll.html   (3369 words)

  
 The Phase-Locked Loop (PLL) page
The Phase-Locked Loop (PLL) is a closed loop frequency control system functioning of which is based on the phase sensitive detection of phase difference between the input signal and the output signal of the controlled oscillator (CO).
And in noisy conditions the behavior of the PLL is stohastic, of course.
In applications the PLL system is often used in combination with the automatic frequency control (AFC) system and/or automatic gain (or signal level) control system.
www.elin.ttu.ee /~min/PLLoop/PLL-PAGE.HTM   (457 words)

  
 Phase-locked loop circuit (US6538519)
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase comparison circuit through a split loop filter.
The first branch of the loop filter includes an integrator filter generating a first error voltage and the second branch includes a low pass filter generating a second error voltage.
As a result the error voltages are effectively summed in the capacitance domain to obviate the need for a dedicated error voltage adder and to allow the total capacitance required in the loop filter to be reduced while still retaining an adequate signal to noise ratio in the filter.
www.delphion.com /details?pn=US06538519__   (325 words)

  
 Magazine
Decision-directed loops and preamble sequences, containing known symbols to aid synchronization, are used for burst modems to quickly acquire a carrier phase for demodulation of a data packet.
While the PLL emphasizes phase lock, it is important to note that this implicitly also means frequency lock, although this is not necessarily true of the reverse.
The PLL is a classic example of a feedback control loop from undergraduate Control Systems 101.
www.commsdesign.com /main/art9711.htm   (2947 words)

  
 All Digital Phase-Locked Loop (ADPLL)
The phase-locked loop (PLL) is used many applications from cellular base stations to industrial systems and processes.
For the locked condition to be attainable, the frequency of the reference signal must be within a defined distance from the free-running or open loop frequency of the NCO, known as the pull-in range.
A PLL is a feedback system that, under certain given conditions, dynamically reduces phase and/or frequency offset between a received signal and a locally generated carrier to zero.
www.altera.com /products/ip/altera/t-alt-adpll.html   (592 words)

  
 The educational encyclopedia, Phase Locked Loop, PLL circuits, Pll theory, VCO
PLL a phase-locked loop is a feedback system combining a voltagecontrolled oscillator and a phase comparator so connected that the oscillator frequency (or phase) accurately tracks that of an applied frequency- or phase-modulated signal.
Phase Locked Loop (PLL) overview of the Phase-Locked Loop (PLL),
PLL 1, PLL 2, PLL 3 PLL 4,
users.telenet.be /educypedia/electronics/pll.htm   (195 words)

  
 Phase Locked Loop
Phase locked loops have always presented a challenge to simulation software because of the convergence problems associated with the control loop.
The demonstration network, PLL.CMP is fully functioning phase locked loop based around a type 1 (exclusive OR) phase detector and a lead-lag compensation filter network to ensure stability.
Also shown is the error signal - it is quite instructive to watch this as the loop actually comes into lock.
www.spiceage.com /Spiceage/pllx.htm   (89 words)

  
 ' + description + '
This is a demonstration of a phase-locked loop being used as an FM demodulator.
The receiver uses a similar VCO that is in the transmitter for the phase-looked loop circuit.
The voltage used to controll the VCO in the PLL is sent to an amplifier and then a speaker.
www.egr.msu.edu /~downeyad/circuits/phaselockloop.html   (190 words)

  
 Digital Phase Locked Loop (phy-pages/dpll.html)
A phase-locked loop (PLL) is an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.
There are many designs of phase locked-loop circuit, but the basics of operation is similar in each case.
The loop starts to track the received signal, and eventually locks-in to the required signal, allowing it to find the center of each received data bit, and reliably decode the received information.
www.erg.abdn.ac.uk /users/gorry/course/phy-pages/dpll.html   (620 words)

  
 Phase Locked Loops
The error signal is integrated by the loop filter and used to control the VCO frequency in such a direction that it corrects for the phase error.
Whenever phase varies, so does the frequency, since the angular frequency is defined as the derivative of phase with respect to time.
The function of the phase detector is to compare the phase of a fed back sample of the VCO signal with that of the reference frequency oscillator.
www.chrisangove.demon.co.uk /ee_ref/plls.htm   (1138 words)

  
 LAB1007 - Phase Locked Loop Basics
The operation of this circuit is typical of all phase locked loops.
The output of the phase detector is a voltage proportional to the phase difference between the two inputs.
Once the PLL is locked and tracking a signal the range of frequencies that the PLL will follow is called the tracking range.
www.lecroy.com /tm/library/LABs/LAB1007   (753 words)

  
 Discover Circuits - Phased Locked Loop (PLL) Circuits
Phase Locked Loop IC As a Communication System Building Block: National Semiconductor Application Note 04-Nov-1995 (added 4/02)
Unlocked PLL Retains Locked Frequency: 07/20/95 EDN-Design Ideas / (added 3/03) Using the PC2 in-phase comparator output, the circuit in Fig 1 keeps the unlocked, or free-run, frequency of a 74HC4046 PLL near the locked frequency.
With the addition of D1, R3, C2, R4, and the 74HC04 inverting buffer, the free-run frequency remains near the locked frequency in the absence of a signal input....
www.discovercircuits.com /P/pll.htm   (311 words)

  
 C5 Programmable Phase-Locked Loop
The Phase Locked Loop is a standard phase- and frequency- locked loop architecture.
The PLL consists of a Reference Divider, a Phase-Frequency Detector (PFD), a charge pump, an internal loop filter, a Voltage-Controlled Oscillator (VCO), a Feedback Divider, and a Post Divider.
The PLL multiplies the reference oscillator frequency to the desired output frequency by a ratio of integers.
www.amis.com /tech_resources/tech_docs/featuresheets/c5pll   (804 words)

  
 Fiber-Optic Phase-Locked Loop Sensitive to Local Strain Only
The apparatus is a fiber-optic phase-locked loop, wherein strain in a multimode optical fiber gives rise to a change in the phase of modulation of a laser beam that propagates along the fiber.
The phases of the fiber-optic-propagated and reference signals are maintained at quadrature by feedback of the DC error voltage to the VCO.
A change (caused by strain) in the phase of the modulation manifests itself as an error voltage and, by virtue of the feedback, is compensated by a change in the modulation frequency.
www.nasatech.com /Briefs/Mar02/LAR15159.html   (580 words)

  
 Phase locked loop IP cuts down jitter: News from True Circuits
technology achieve lock in essentially constant time at a particular output frequency independent of feedback divider and bandwidth settings, regardless of the loop bandwidth for a given output frequency, and add no additional frequency overshoot.
PLLs can typically expect two or more orders of magnitude improvement in lock times with the same level of input period jitter rejection as before.
True Circuits' low-jitter spread spectrum PLL allows the spread-spectrum functionality to be included in the ASIC rather than requiring a separate part on the system board, thus reducing manufacturing costs.
www.electronicstalk.com /news/tue/tue101.html   (625 words)

  
 Electronics 12
The phase-locked loop compares the phases of the input signal and the oscillator signal, and adjusts the oscillator to reduce the phase difference.
The output of the phase detector is usually in the form of pulses that have to be low-pass filtered by the loop filter, the middle block.
Notice the phase relation between Ch 1 and Ch 2 as the frequency is varied; it is not zero, and must increase to raise the VCO control voltage.
www.du.edu /~etuttle/electron/elect12.htm   (3473 words)

  
 phase locked loop
The other input to the phase detector is the reference signal, which we wish to lock the frequency of the VCO to.
If there is a difference in frequency or phase between the two inputs then an error signal is produced at the output of the phase detector.
This ensures that the local oscillator is at the same frequency and in phase with the remote one.
ourworld.compuserve.com /homepages/g_knott/elect138.htm   (305 words)

  
 Phase-Locked Loop (PLL) Definition
The phase-locked loop (PLL) block is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal.
In this locked condition, any slight change in the input signal first appears as a change in phase between the input signal and the oscillator frequency.
This phase shift then acts as an error signal to change the frequency of the local PLL oscillator to match the input signal.
www.altera.com /support/software/nativelink/quartus2/glossary/def_pll.html   (204 words)

  
 Phase-Locked Loop (Communications Blockset)
The Phase-Locked Loop (PLL) block is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal.
Implement a phase-locked loop to recover the phase of the input signal
You specify characteristics of the VCO using the VCO quiescent frequency, VCO initial phase, and VCO output amplitude parameters.
www.ece.umr.edu /computing/unix/software/matlab/toolbox/commblks/phaselockedloop.html   (261 words)

  
 Panaxis FMX PLL FM Exciter Review
The loop locks within a couple of seconds, this is indicated by the loop lock LED glowing brightly.
The loop reference signal is 100KHz, as became evident during the RF tests, as it's all over the RF output signal.
This DC feedback path enables the output frequency to be locked to the frequency of a stable crystal reference oscillator.
www.irational.org /sic/radio/panaxis-fmx.html   (2036 words)

  
 74HC4046 phase-locked-loop
This is a relatively simplistic explanation of a phase-locked-loop (PLL) with a vco because whole books have been devoted to phase locked loops offering varying degrees of mathematical complexity.
This is a rather simplistic explanation of a 74HC4046 phase-locked-loop (PLL) with a vco because whole books have been devoted to phase locked loops, offering varying degrees of mathematical complexity.
It compares the phase relationship between the reference signal on pin 14 of the 74HC4046 "Sig In" pin with the input frequency on pin 3 "Comp In".
www.electronics-tutorials.com /devices/74hc4046.htm   (1833 words)

  
 Circuit Sage: Phase Locked Loop Tools and Links
National's PLL Design Software: A change from their old routine to be much more powerful and completely web based.
PLL Design Assistant, from Mike Perrott at MIT, software for allows fast and straightforward design of PLLs at the transfer function level.
PLL design one, two, three by Mark Curtin and Paul O'Brien at Analog Devices.
www.circuitsage.com /pll.html   (776 words)

  
 Agilent Phase Locked Loop (PLL) DesignGuide
Using a dialog box of Phase-Locked Loop schematics, you select your desired PLL configuration - frequency synthesizer, frequency modulator or phase modulator.
You can use the optimization templates to define the loop performance, then proceed to evaluate the phase noise response and transient response.
The PLL configuration, simulation technique, and type of phase detector and low-pass filter categorize the simulation set-ups.
eesof.tm.agilent.com /products/e5600a_pll.html   (187 words)

  
 Phase Locked Loop : FUJITSU Singapore
At 2.7V, the supply current exhibited by Single PLL is typically 2.0mA while it is 3.0mA for Dual PLL.
Both the Single PLLs and Dual PLLs are fabricated using Fujitsu’s BICMOS technology.
The Dual PLLs are fabricated using Fujitsu’s BICMOS technology.
www.fujitsu.com /sg/services/micro/semiconductor/assp/pll   (159 words)

  
 Fictionwise eBooks: Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Second Edition by D. Stephens
Techniques to analytically estimate the phase noise of a divider; - Presentation of optical phase-locked loops with primers on the optical components and fundamentals of optical mixing; - Section on automatic frequency control to provide frequency-locking of the lasers instead of phase-locking; - Presentation of charge pumps, counters, and delay-locked loops.
Perhaps most distinctive is the chapter on optical phase-locked loops that begins with sections discussing components such as lasers and photodetectors and finishing with homodyne and heterodyne loops.
Phase-Locked Loops for Wireless Communications: Digital, Analog and Optical Implementations, Second Edition
www.fictionwise.com /ebooks/eBook11313.htm   (307 words)

  
 Definition: phase-locked loop
Note: Phase-locked loops are widely used in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
phase-locked loop (PLL): An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.
www.atis.org /tg2k/_phase-locked_loop.html   (81 words)

  
 CommsDesign - ParthusCeva offering 0.13-micron phase-locked loop cores online
But at the end of the day 90 percent of PLL users just want a good, stable device that locks at their desired clock frequency and offers some flexibility in case they need to change those clocks for some reason.
PLL designs for each process are validated by a compiler calibration chip.
Available PLL cores are also characterized by foundry processes, including the 0.25-, 0.18- and 0.13-micron processes of TSMC, United Microelectronics and Silterra Malaysia.
www.commsdesign.com /news/product_news/OEG20030414S0026   (672 words)

  
 Phase Locked Loop Analysis and Synthesis
PLL is a DOS program that plots the frequency response, impulse, and step response of simple phase-locked loops.
The user has a choice of five loop filters and can select component values arbitrarily, or can have the computer choose the component values based on desired loop bandwidth and damping factor.
Notice that the adjacent channel settling time and the peak frequency overshoot is automatically computed.
members.tripod.com /michaelgellis/pll.html   (106 words)

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