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Topic: Placement (EDA)

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	SOCcentral: Hard Macro Placement in Complex SoC Design (SOCcentral 17008)
		Relative placement constraints, alignment constraints, grouping constraints, and region constraints could be defined prior to placement and honored during the optimization process.
		Placement and floorplanning tools developed to handle standard cells, alone, cannot produce best area and timing results, due to the implementation challenges presented by hard macros.
		To be effective, floorplanning placement engines must now incorporate cost functions to address the new challenges presented by having 100s or 1000s of hard macros in a design.
	www.soccentral.com /results.asp?CategoryID=488&EntryID=17008 (3263 words)

	EDAC
		EDA software tools or tool suites which may display simulator output for analysis (as in waveform analyzers) or which may analyze the reliability, electromagnetic interference, metal migration, signal integrity, or thermal characteristics of a design.
		EDA products and services are essential for the design of electronic products that enable many other high-tech sectors of the economy, such as computers, communications, consumer, industrial, military/aerospace, semiconductors, and transportation.
		EDA software tools that provide an environment where issues such as timing, area, power dissipation, and routeability can be analyzed before a detailed physical layout of a design is completed.
	www.edac.org /industry_glossary.jsp (6081 words)

	EDA Staffing Inc.
		EDA has been a leader in servicing high technology and industrial companies in the New England area since its inception in 1976, with both a permanent and temporary staffing division.
		In addition to permanent placement, EDA's temporary contract services division is prepared to respond immediately in supplying personnel on a temporary basis.
		Along with EDA's experience and track record, we are equipped to staff engineering and design drafting personnel with a computer and CAD software (AutoCAD and Cadra) for the temporary employee to use for the duration of the contract.
	www.eda1.com (306 words)

	VEDA - VLSI Engineering&Design Automation
		In the case of candidates who are adjudged as extraordinarily brilliant/bright by the selection committee, some of the associated companies can offer a placement (subject to successful and satisfactory completion of the course) with either full /partial waiver of fee.
		It also has conducted several Advanced Diploma Programs in logic and physical design areas of VLSI and embedded system design, where almost all the trainees are absorbed by the industry.
		On the infrastructure side, VEDAIIT has sufficient licenses for most of the EDA tools from leading EDA tool vendors like Cadence, Synopsys, Synplicity, Mentor, Altera, Verisity etc. VEDAIIT is recognized as a Regional Academic and Research Partner of excellence in VLSI Engineering and Design Automation by Sun Microsystems.
	www.vedaiit.com /faqs.html (826 words)

	Bartels AutoEngineer User Manual - Autoplacement
		The placement algorithms are guarded by adjustable strategy parameters for net list preference control and for the consideration of part segment matching/fitting.
		On incomplete initial placement it is recommended to change placement parameters (use smaller placement grid, reduce part expansion, use unrestricted part rotation, allow SMD mirroring; see below on how to set placement parameters) and restart the autoplacer (after Undo and/or selecting a different placement start point) to achieve 100% part placement.
		Placement optimization can be interrupted at any time by pressing an arbitrary key on the keyboard.
	bartels.de /baedoc/bm4_04_en.htm (2994 words)

	Proteus EDA/CAD - PCB Design Software (Site not responding. Last check: 2007-10-21)
		Placement resolution is 10 nanometers within a maximum board size of 20m.
		During the placement phase, ARES displays both the ratsnest and force vectors.
		All computation is based on grid-less shape geometry and occurs in the background so that there is interference in manual board placement for computationally intensive layouts.
	www.labcenter.co.uk /products/pcblayout.htm (1224 words)

	Timing Closure at the Crossroads (Site not responding. Last check: 2007-10-21)
		One approach traditional EDA companies have taken is to inject floorplanning and/or placement information during the functional-design phase.
		For example, Synopsys' unified synthesis and placement methodology moves placement to the front-end of IC design and provides for fewer iterations and faster timing closure.
		This includes traditional EDA companies that are developing new strategies that "stand on the shoulders" of the tried-and-true approaches.
	www.techonline.com /community/related_content/5966?print (958 words)

	EDA start-up seeks to fill IC 'empty space'
		SANTA CRUZ, Calif. — Current IC placement techniques leave large amounts of empty space on chips—and an EDA startup is promising to do something useful with it.
		It distributes placement and routing tools from Seiko Instruments' EDA division, which in turn distributes Apex's tools in Japan.
		Empty space emerges not only because chips are pad-limited, but because the top-down partitioners used by current placement algorithms leave large amounts of empty space behind, Ku said.
	www.eedesign.com /article/printableArticle.jhtml?articleID=17408258 (510 words)

	EETimes.com - Sapphire presents new IC design approach (Site not responding. Last check: 2007-10-21)
		Sapphire holds there is no compelling need to bring placement data into synthesis, that interconnect optimization should occur after synthesis, and that placement and routing do not need to come from the same vendor.
		EDA industry leaders are trapped in a "die-size-centric" way of thinking, said Shashank Goel, Sapphire's president and CEO.
		The result is much faster than quadratic placement, he said, with better results and an ability to handle larger circuits.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=18301659 (1314 words)

	Pro Innovation (Site not responding. Last check: 2007-10-21)
		The desktop EDA industry is almost 20 years old and several mainstream EDA vendors have slowed RandD, resulting in a lack of innovation and stagnant software.
		Not only is Electronics Workbench introducing an abundance of productive features new to EDA design, but our products are also evolving and improving at a pace unmatched in the industry.
		Our 15 years of EDA experience combined with a modern architecture and today’s best software engineering practices have allowed us to build the industry’s most innovative, efficient capture tool.
	www.interactiv.com /html/proabt3.html (538 words)

	Synplicity: Products
		Your responsiblities include: developing and supporting mapper software; identifying opportunities and implementing optimization strategies; characterizing the device timing and correlating the timing between synplify and vendor tools; functional testing the mapper using existing regression test mechanism; working collaboratively with different functional groups and vendors to coordinate development work.
		Appreciate the placement of a design and the timing estimationAnalyze designs from diverse technologies (FPGA Altera or Xilinx)Functional and Flow testing of the placement and synthesis algorithms, and their documentationDefine and implement a timing or/and area optimization using placement information
		Familiarity with placement and synthesis algorithms and data representations preferred.
	www.synplicity.com /corporate/careers/design.html (489 words)

	Bartels AutoEngineer User Manual - General
		There are no restrictions at the definition and placement of pads, copper areas, parts, traces, texts, etc. The user interface provides a genuine display even for the more complex structures such as circles or arcs.
		Matrix placement is intended especially for the initial placement of homogeneous part types such as memory devices, block capacitors, test points, etc. Of course the matrix placement function also considers the default rotation angle and mirror mode settings.
		Initial placement functions are provided for performing a complete placement by automatically placing not yet placed parts inside the board outline.
	bartels.de /baedoc/bm4_01_en.htm (6915 words)

	The EDACafe.com Marketing Machine
		EDACafe.com reaches out to more EDA professionals than any other EDA site.
		EDA professionals count on us for the latest industry news and up-do-date technical information.
		These include the world's most complete EDA product catalog listings, technical papers, EDA news, CEO interviews, multimedia presentations, priority press releases, event postings, job placement and more.
	www.edacafe.com /media_kit (330 words)

	EDA earns high satisfaction rating (Site not responding. Last check: 2007-10-21)
		According to a national survey of students from nine doctoral programs in educational administration, graduates from the UK College of Education's Department of Administration and Supervision (EDA) reported that they finish their degrees quickly and receive top quality mentoring, career guidance, and job placement.
		In fact, the EDA department at UK received higher scores than four universities which are among those the Kentucky Council for Post-Secondary Education targeted as benchmarks for UK - University of Texas at Austin, The Ohio State University, University of Michigan at Ann Arbor, and University of Wisconsin-Madison.
		In personal accounts, students have commented that the EDA program prepared them well for their career primarily because the department’s faculty had formerly served as school administrators.
	www.uky.edu /Education/news/high_rating.html (322 words)

	Open-source project looks to ignite EDA research (Site not responding. Last check: 2007-10-21)
		The goal: to revitalize the connection between universities and the EDA industry.
		While OpenAccess promises a standard data model for IC design tools, it also provides a database that can be used by university researchers and students who want to develop new algorithms without writing complete tools.
		If a researcher wants to experiment with timing-driven placement, for example, he or she will need not only a database but a timing engine and a GUI.
	www.eedesign.com /article/printableArticle.jhtml?articleID=57701868 (532 words)

	39th DAC Web Booth for Tanner EDA
		Tanner EDA is the market leader in IC physical design software for Windows®, with affordable solutions for analog/mixed-signal IC design.
		Tanner EDA is a division of Tanner Research, Inc; a privately held company headquartered in Pasadena, California.
		Tanner EDA was the first company to develop innovative IC design software for the PC, and the company still specializes in producing IC design software for Windows® platforms that is affordable and easy to use.
	dac.com /39th/39exhibitorArea.nsf/0/C408269F6622D24487256B65007977E7 (396 words)

	Welcome to EDACafe, the Leading EDA Portal
		EDA Portal, EDA News, EDA Jobs, EDA Presentations, EDA Newsgroups, Electronic Design Automation.
		Survey for engineers using EDA tools for SI and PI
		Commentary: EDA Industry Update May 2006 -- What did the Last Quarter Bring?, Internet Business Systems...
	www.edacafe.com (1507 words)

	PRESS RELEASE DesignAdvance Announces VP Sales, Seasoned Exec Howard Coltin Joins to Promote Faster PCB Component ... (Site not responding. Last check: 2007-10-21)
		Coltin is a veteran of the design automation industry, having over 17 years of sales and management experience with EDA and CAD companies.
		CircuitSpace's intelligent and interactive component placement technology will have a dramatic impact on the PCB design process.
		DesignAdvance Systems, Inc. develops automated EDA and CAD design-synthesis software tools that reduce the amount of time it takes to design electrical and mechanical products.
	www.marketwire.com /mw/release_html_b1?release_id=89602 (474 words)

	DeepChip Homepage
		I lead the softblock "placement through routing" effort in which PhysOpt was used to perform the initial placement, placement of ECO cells (both timing and functional), and to incrementally fix setup and hold violations for all 15 softblocks.
		A technique we used to save run time for the 1.4 Mgates module during placement was to turn off the area recovery mode.
		Since a lot of our placement was performed with beta versions and since we froze PhysOpt at revision 1.1d, these may already have been resolved in the newest version of PhysOpt.
	www.deepchip.com /posts/0360.html (6550 words)

	Product Listing: IC Physical Design Tools
		Each product is delivered with a complete set of views and models for leading EDA tools.
		The result is a widely-used set of libraries that offer a wide range of performance and density choices.
		Blast Chip is the industry's only synthesis, place and route solution that does not rely on inaccurate wire load models or initial placement data to determine cell size.
	ecat.edacafe.com /product_list.php?category_id=1000048 (3173 words)

	DBX2Sheets Schematic Sheet Utility (Site not responding. Last check: 2007-10-21)
		When preparing multi-sheet schematics in ACCEL EDA Schematic, it can be difficult to maintain the 'Sheet Number' and Number of Sheets' fields.
		One must manually place these fields, and then if a mistake is made in placement, move them manually to the desired position.
		It relies on the placement of the first page 'Sheet Number' and 'Number of Sheets' fields, and then will automatically 'ADD', 'MOVE' or 'DELETE' the other pages based on the placement of these fields on the first sheet.
	lonestar.texas.net /~joj/21000.html (161 words)

	EDA Software -- ORCAD hints
		Also standard.tpl had a number of free track obstacles defined (two 8mil vertical bars on either side + 4mil circles on each corner of board).
		To add fudicials, grd strips or holes go right click when component placement tool selected, choose "layout" footprint library then select desired object to add.
		Use "place any" selection during placement to show dialog box of all un-placed parts.
	www.ncf.carleton.ca /~ap389/index_files/orcad_hints.htm (1015 words)

	Mentor Graphics Strengthens its SoC Leadership With New TeraPlace Physical Implementation Tool Suite
		Extending traditional placement to include virtual routing, extraction with delay calculation, timing analysis and optimization, the Mentor Graphics® TeraPlace tool suite is comprised of TeraPlace, for innovative timing-driven placement and two plug-in options -- TeraOptimize(TM), for physical optimization and TeraCTS(TM), for Clock Tree Synthesis.
		By extending the traditional physical design link between placement and detailed routing, and providing accurate parasitic information earlier in the process, the tool suite delivers a highly integrated physical implementation solution that allows design teams to overcome the inconsistency of existing place and route solutions to reach timing closure.
		TeraPlace then verifies final placement with a virtual router that replaces inaccurate assumptions and estimations of wire load models with accurate parasitic data.
	www.design-reuse.com /NEWS/news17_04_00_3.html (900 words)

	gmane.comp.lang.c2.devel
		For uninitiated, placement new expression takes an additional argument: the memory address on which the object will be constructed.
		The trade off is that the programmer must guarantee that the pre-allocated storage is sufficiently large and that it meets the memory alignment requirements.
		Below is a list of issues to consider when using placement new in C2: 1) If the entity is a non-array object, the placement new-expression returns a reference to any-store object.
	blog.gmane.org /gmane.comp.lang.c2.devel (1390 words)

	Ultiboard PCB Layout (Site not responding. Last check: 2007-10-21)
		For connections and other parts requiring precise placement, you can enter exact coordinates.
		Once placed, critical shapes can be locked so they will not be moved by the push and shove routine.
		Ultiboard's "jump-to-error" feature allows you to click on a design rule violation in the error log and have Ultiboard automatically jump to the position on the board where that problem occurred.
	www.ultiboard.com /u_board.html (685 words)

	Franz Inc Customer Applications: EDA/Semiconductor
		Top-Down DP begins the initial phase of the floor plan design, allowing the user to start accounting for the physical floor plan even during the early phases of behavioral design using a hardware description language.
		Logic DP starts with the gate level net list obtained from Top-Down DP and ends at the point where real placement occurs.
		Physical DP begins with the full placement obtained with Logic DP and ends with the full routing of cells and thereby full routing of the circuit.
	www.franz.com /success/customer_apps/eda (312 words)

	Pantheon Interfaces to Schematic Entry Applications, Create or Load Design Geometries, Rules-Based Component Placement (Site not responding. Last check: 2007-10-21)
		You can associate components with placement class rules that define the minimum allowed component-to-component placement clearance.
		Options for displaying components make the layout process straightforward: highlight net connections associated with selected components; highlight components by reference, class, or group; or specify the component elements to display during placement, such as clearances or outlines.
		As an electronic design automation (EDA) company, Intercept develops the high technology PCB software design applications necessary to create printed circuit boards, hybrids, and multi-chip modules.
	www.intercept.com /html_files/products/products_pantheon_features2.htm (340 words)

	Careers and Resources -- Information Technologies - (Site not responding. Last check: 2007-10-21)
		Inspired IT Recruitment - UK Specialists in the placement and recruitment of IT Professionals.
		IT Network Wales - A summer placement programme providing employment for students in further education.
		WA Consultants Ltd - Exeter based IT recruitment specialist jointly focused on contracting and permanent placements.
	www.edinformatics.com /careers/computer_systems.htm (2340 words)

	Products and Services - Association of Protel EDA Users
		It streamlines the placement process and offers a rich set of placement rules.
		Each of these classes may have different rules and even be displayed in different colours.
		Powerful placement algortithms include interactive component shoving, splashing a nudging.
	www.techservinc.com /protelusers/prodserv.html (227 words)

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