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Topic: Planar process

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	The Chip Collection - STATE OF THE ART - Smithsonian Institution
		This process, which led directly to the creation of the commercially viable integrated circuit, is a form of contact printing.
		For all the manufacturing benefits brought about by the mesa process, it had two major drawbacks: the mesa was susceptible to both physical harm and contamination, and the process didn't lend itself to the making of resistors.
		(The base was composed of negatively doped silicon, the collector and emitter of positively doped silicon; the first planar device was thus a pnp transistor.) Then he covered the whole thing with a protective coating of silicon dioxide, an insulator, leaving certain areas in the base and the emitter uncovered.
	smithsonianchips.si.edu /augarten/p8.htm (520 words)

	Method and apparatus for drying parts and microelectronic components using sonic created mist - Patent 5653045 (Site not responding. Last check: 2007-11-01)
		More particularly, the planar process involves the proper sequencing and repetition of the steps of oxidation, patterning, dopant-addition and dopant diffusion, which results in the selective introduction of p- and n-type dopant atoms into specific regions on the surface of the wafer.
		From a processing standpoint, the key steps in the planar process are: 1) the formation of a masking oxide layer; 2) the selective removal or etching of the oxide layer; 3) the deposition of the dopant atoms on or near the wafer surface; and 4) the diffusion of the dopant atoms into the wafer surface.
		The first step of the planar process is the growth of an oxide layer of about 20 nanometers to 1 micrometer in thickness on the surface of the wafer.
	www.freepatentsonline.com /5653045.html (6523 words)

	Publishing (Site not responding. Last check: 2007-11-01)
		Planar technology, based on external formation, requires a certain sequence of interactions between the structured medium and the object being formed, in which the configuration of the region to be formed and it position are defined by the structure of a media and its alignment with the object.
		Planar technology for manufacturing of semiconductor devices and integrated circuits is defined by technological cards ranking operations of technological processes, topological drawings defining localisation of these processes in space, and routing cards determining sequence of technological processes, i.e.
		The distance between two planes is determined by the processes of insertion or by the coating of thin films, whereas the configuration of a structure in a plane is created by the lithography process: photolithography, X-ray lithography, electron- or ion-beam lithography.
	msi.lms.lt /rtdresult/self_e.html (5417 words)

	Planar deep oxide isolation process utilizing resin glass and E-beam exposure - Patent 4222792 (Site not responding. Last check: 2007-11-01)
		A planar isolation process for providing silicon dioxide in deep wide trenches in a planar surface of a monolithic silicon semiconductor substrate, as recited in claim 3, said process being further characterized in that the trenches are in the order of 2 to 50 microns wide and in the order of 4 microns deep.
		A still further object of the invention is to provide an improved planar deep oxide isolation process wherein resin glass is utilized as an e-beam resist and as the oxide isolation in deep trenches.
		The inventive process is unique in that it combines the use of resin glass as an e-beam resist and as the oxide isolation for deep trenches.
	www.freepatentsonline.com /4222792.html (4636 words)

	The Planar Process
		Under the mesa process the oxide layer was deposited on after the making of the base in order to mask the emitter diffusion and was later removed.
		This went against all accepted knowledge in the silicon community: It is widely believed at the time among practitioners of the silicon art that the oxide layer used to mask dopants was dirty and, as a result, had to be etched away.
		As the boron atoms diffused both vertically and horizontally, the junction between the collector and the base moved laterally and was protected from outside contaminants by the oxide layer.
	nobelprize.org /nobel_prizes/physics/articles/lecuyer/planar.html (405 words)

	Buy Planar Products Direct From the Manufacturer
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		Planar will disclose your information when we believe in good faith that it is legally required, such as pursuant to a warrant, subpoena, or court order, or to protect our rights and property.
		Planar strives to provide a commercially reasonable degree of security, but does not guarantee that such measures will be effective.
	www.planaronline.com /privacy (1136 words)

	Earthquake - Wikipedia, the free encyclopedia
		To describe the physical process of occurrence of an earthquake, seismologists use the Elastic-rebound theory.
		Data are received through a questionnaire on the Internet answered by people who actually experienced the earthquake, reducing the process of preparing and distributing a map for a particular earthquake from months to minutes.
		They are used by insurance companies to set insurance rates for properties located in earthquake-risky areas, by civil engineers to estimate the stability of hillsides, by organizations responsible for the safety of nuclear waste disposal facilities, and also by building codes developers as the basis of design requirements.
	en.wikipedia.org /wiki/Earthquake (2665 words)

	Moore_Law
		The planar process was a logical outgrowth of the diffusion and oxide masking process.
		Using a lithographic process of a series of etched and plated regions on a thin, flat surface or wafer of silicon, the "chip" was born out of the planar transistor.
		Many process changes contributed to this, not the least of which was moving to optical projection rather than contact printing of the patterns on the wafers.
	research.microsoft.com /~gray/Moore_Law.html (11309 words)

	Planar: Planar.com Privacy Policy
		Additionally, Planar may use your financial and contact information internally for purposes such as marketing, customer administration, and technical administration of the Planar Site.
		Planar uses great care in selecting business partners with whom we share your information.
		However, Planar is not a guarantor of outside parties' practices regarding your information.
	www.planar.com /globalnavinfo/privacy (1131 words)

	Benefits of Spherical Semiconductor Technology (Site not responding. Last check: 2007-11-01)
		A streamlined process that shaves a day or two off of the cycle time could mean the difference between several hundreds of thousands of dollars of profit and several million dollars.
		The majority of semiconductors made are flat, rectangular, and planar (two-dimensional) – a design that seems to be the simplest to work with, but one that has many disadvantages.
		In sum, though planar technology has been the prevailing technology for semiconductor manufacturing, spherical technology promises many incredible benefits that deserve attention.
	mason.gmu.edu /~hdinh/researchdraft.html (1565 words)

	Physical Fabrication of Transistors
		In the mesa transistor, the diffusion process has been used to create the base layer, and a central emitter region created by either alloying in an emitter, or diffusing in another layer of opposite type to the base layer, and making a contact to it.
		The planar fabrication process (which, unlike the mesa process, did not need to isolate the parts of the silicon wafer where the transistor was fabricated with an etched trench) enabled multiple transistor structures to be fabricated on the same silicon wafer, and they could if desired be interconnected using the aluminium metallisation layer.
		Note that a key feature of the planar epitaxial process is the use of layers of non-conducting oxide or nitride during the photolithographic stages.
	www.cjseymour.plus.com /elec/basicfab/fab.htm (5148 words)

	Method of producing planar metal-to-metal capacitor for use in integrated circuits - US Patent 6069051 (Site not responding. Last check: 2007-11-01)
		The method provides a simpler process which has a better yield and more reliable structure by creating a metal-to-metal capacitor on a planar surface, not in deep trenches.
		In addition to the process simplicity, the method also allows the use of any dielectric materials which are needed by the product designer; e.g., higher or lower dielectric constant and also not limited by high etch rate difference.
		Because the inventive process is a planar process, there are no corners in the bottom of deep trenches to cause yield and reliability problems.
	www.patentstorm.us /patents/6069051.html (333 words)

	Chapter Six
		As the planarity decreases, the capacitance rises to approximately the same level as for the other offsets, but is more dramatic due to the lower initial value.
		The original planar structure was generated using the reduced interlevel dielectric technology file developed for the Rockwell process.
		The planarity and separation values are not based upon experimental data and are intended to provide information regarding the general trends of the conductors rather than realistic parasitic capacitances.
	www.ecse.rpi.edu /frisc/theses/CampbellThesis/chapter6.html (8668 words)

	Vision (Site not responding. Last check: 2007-11-01)
		Planar Process is an outstanding example of how multiple disciplines combine to yield a usable result.
		Micro chemistry and micro biotechnology exercises are also possible in miniture reactors fabricated using planar process techniques.
		A fundamental understanding of planar processing is essential to enable skills growth commensurate with industry needs.
	www.modu-lab.org /Modulab/tsld010.htm (253 words)

	course notes
		In 1959 Noyce filed a patent for a planar process for coating a layer of oxide over silicon.
		The oxide layer in the planar process meant that transistors could be linked without the need for wires.
		It would be far better, he reasoned, to use the planar process to produce a general-purpose circuit which could then be programmed to perform required functions.
	perso.wanadoo.es /nickjs/coursenotes.htm (566 words)

	Elliot Hui - 3-D microfabrication
		Thus, while three-dimensional structures are often desirable, it is a challenge to microfabricate in three dimensions without losing the manufacturing advantages of lithography.
		The pop-up mechanisms of children's storybooks achieve assembly of complex 3-D structures out of planar elements initially parallel to one another with a quick simple motion, the turn of a page.
		We have formed conformal films of carbonized parylene, resulting in sub-micron molding precision and a release process that is dry, rapid and extremely selective, allowing large structures to be released without damage.
	www-bsac.eecs.berkeley.edu /archive/users/hui-elliot (203 words)

	MIT EECS Event (Site not responding. Last check: 2007-11-01)
		The process combines (1) gate length controlled precisely through a film thickness, independent of lithography and etch (2) high-quality gate oxide grown on single-crystal Si, and (3) self-aligned source and drain extensions.
		The process can be extended to a complete CMOS process only modestly more complex than the current planar process.
		The circuit density is similar for planar and VRG CMOS, limited primarily by lithography.
	www.eecs.mit.edu /AY99-00/events/76.html (200 words)

	Integrated Circuit Process (Site not responding. Last check: 2007-11-01)
		With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in...
		An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost.
		Damascene An integrated circuit process where a metal conductor pattern is embedded in a dielectric film on the silicon substrate, resulting in a planar interconnection layer.
	www.bocamicro.com /integratedcircuits/integratedcircuitprocess (1576 words)

	Planar: Planar Innovations include Atomic Layer Deposition (ALD) and stereoscopic displays.
		The SD line of stereo displays from Planar is the next generation in stereoscopic monitors.
		Planar has addressed these problems with an innovative type of stereo display making use of proprietary StereoMirror™ technology and high quality Planar monitors to give viewers the ultimate in stereo viewing pleasure.
		The ALD process uses typically two chemicals to create alternate, saturated, chemical reactions on the surface, resulting unique self-limiting growth with many excellent features like conformality, uniformity, repeatability and accurate thickness control.
	www.planar.com /advantages/innovation (323 words)

	Wet powder spraying
		A suspension composed of solvent, powder and additives is sprayed by a nozzle.
		The major advantages of WPS compared to screen printing or plasma spraying are the low-cost fabrication, the flexibility concerning size and shape of the samples to be coated, and the easy integration into an industrial process chain.
		Limitations of the technology are the overspray (the amount of suspension which is sprayed besides the sample) and the formation of a suspension mist which needs to be extracted by suction.
	www.fz-juelich.de /iwv/iwv1/index.php?index=77 (245 words)

	50811 (Site not responding. Last check: 2007-11-01)
		This project will investigate the use of planar processing techniques for fabricating large area APDs and APD arrays.
		During Phase I, large area APDs and arrays using the planar process were successfully fabricated.
		Simulations of processing and device performance will be conducted and applied to the APD design.
	www.science.doe.gov /sbir/awards_abstracts/sbir/cycle16/phase2/43.htm (205 words)

	Modu-Lab: Low Cost Laboratory Equipment for Introductory Planar Process
		In order to rate, in global competition, it is essential to bring a large number of high quality manufacturing technicians to the industry in a very short period of time.
		The nature of the IC (integrated circuit) fabrication process is highly complex and absolutely intolerant of mistakes.
		Having students with experience in the basic principals of planar process - Oxidation/Diffusion, Photolithography (spin/bake/expose/develop), Etch, and Vapor Deposition - before they are allowed in the advanced lab makes sense.
	www.emsi-usa.com /prod04.htm (513 words)

	Characterization of a new planar process for implementation of p-on-n HgCdTe heterostructure infrared photodiodes ...
		Characterization of a new planar process for implementation of p-on-n HgCdTe heterostructure infrared photodiodes
		In summary, we have demonstrated the feasibility of fabricating planar HgCdTe heterostructure photodiodes of a p-on-n configuration.
		This planar process has substantial potential for LWIR HgCdTe, because it could simplify FPA processing.
	www.findarticles.com /p/articles/mi_qa3776/is_200106/ai_n8990787 (410 words)

	Swiss Lab - suppliers of laboratory and process analysis equipment (Site not responding. Last check: 2007-11-01)
		Swiss Lab specializes in the supply and service of Laboratory and Process analysis equipment in Southern Africa.
		The company is the exclusive agent for: Metrohm, Anton Paar, Camag, Grabner, Steinfurth, Cole Parmer, Eco Chemie, Applikon and Behr.
		Brand names such as Anton Paar, Applikon, Cole Parmer, Camag, Grabner, Metrohm, Behr, Eco Chemie and Steinfurth are supplied, along with a whole range of other laboratory equipment.
	www.swisslab.co.za /testing-equipment.html (183 words)

	A Sub-40nm Nanostructured La0.7Sr0.3MnO3 Planar Magnetic Memory
		A single-step nanolithography planar process, which allows generating the core-element of a spin-polarized magnetic memory in the fully spin-polarized La0.7Sr0.3MnO3 (LSMO) manganite, is reported.
		Taking benefit of the proximity effects due to backscattered electrons, a conventional electron-beam patterning process at 30 KeV has been optimized to generate sub-50 nm-wide nanokinks in the magnetic microbridge.
		The best layout for the nanokinks, the electron beam patterning parameters and the results of the ion beam etching (IBE) for transferring these nanopatterns in the magnetic oxide are reported.
	www.nsti.org /Nanotech2004/showabstract.html?absno=342 (101 words)

	ArtLex's Pin-Pl page
		This distant relative to archaeology might be called "urban beachcombing." The process of discovery becomes part of finished objects.
		This is often done to silver when either raising, sinking or embossing it.
		Lithography and offset are both planographic printing processes.
	www.artlex.com /ArtLex/Pin.html (3071 words)

	Modu-Lab - Microelectronics / Microfabrication Lab Equipment Designed for Colleges and Universities
		This site is dedicated to the memory of JEAN HOERNI, 1924-1997 - The inventor of planar process and the godfather of the integrated circuit.
		The individual process steps can inspire whole volumes of insight and expertise; but, the overall procedure remains pretty much the same -- Deposit, Pattern, Etch, Repeat.
		Please bear in mind that the permutations of this simplified outlook are virtually endless given the selection of materials and, most importantly, the patterns utilized.
	www.modu-lab.org (439 words)

	Book Reviews
		Topics include electrostatics, capacitance and energy storage, applying electrostatics to practical processes, practical shielding of instruments, the differential amplifier, general application problems, shielding in resistance-bridge systems, magnetic processes in instrumentation, RF processes in instrumentation, and the earth plane.
		The objective of this textbook is to introduce the reader to the subject of power electronics, presenting the basic processes of efficient energy conversion by electronic means through the use of power semiconductor switches.
		This book is aimed at design engineers and process engineers in semiconductor houses, specializing in the fabrication of power circuits, and at application engineers in system houses, where power electronics is relevant in the design of an electronic system.
	www.powerdesigners.com /InfoWeb/library/book_reviews.shtml (7790 words)

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