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Topic: Positive Referenced Emitter Coupled Logic

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mathematical logic

logic gate

logical positivism

symbolic logic

intuitionistic logic

fuzzy logic

Combinatory logic

modal logic

logical argument

Logical disjunction

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	Buffer Types
		Emitter-Coupled Logic is based on the use of a multi-input differential amplifier to amplify and combine the digital signals, and emitter followers to adjust the dc voltage levels.
		In operation, a logical ouput changes state by only 0.85 volt, from a low of -1.60 volts to a high of -0.75 volt.
		The HSTL nominal logic switching range is 0.0 V to 1.5 V, resulting in faster outputs with reduced power dissipation, and minimized EMI concerns.
	www.andreas-schwope.de /ASIC_s/Schnittstellen/Buffer_Types/body_buffer_types.html (2093 words)

	Low voltage non-saturating logic circuit technology - Patent 4962341
		Emitter coupled logic (ECL) is a family which uses bias circuitry which is separate from the power supply for the transistors performing the logical switching operations.
		One logical input 306 is the input to inverter 301.
		The emitter resistors, such as 239, 251, 251a, and 251b have associated resistances of approximately 100 ohms which cause an increase in the emitter voltage in the on condition to thus provide a base-emitter bias voltage of approximately 800 mV in the on condition and approximately 650 mV in the off condition.
	www.freepatentsonline.com /4962341.html (20326 words)

	Line feed circuit with logic level controlled ringing - Patent 5659608
		One of the logic level signals is a 20 Hz clock signal with a duty cycle of 20 ms high and 30 ms low.
		A positive level of approximately 6 volts therefore appears at the output of operational amplifier OAD and this output is applied to the inverting input of operational amplifier OAC via resistor R111.
		Operational amplifier OAC compares this positive output level with the signal applied at its non-inverting input from resistor R109 which is connected to the junction of resistors R108, R138 and the collector of transistor Q103.
	www.freepatentsonline.com /5659608.html (4870 words)

	Reactive coupled drive circuit for magnetic bubble memories - United States Patent 3,934,235
		Accordingly, a prime feature of this invention is the combination of a reactive coupled pair of tuned circuits and a magnetic bubble memory in which bubbles move responsive to a magnetic field provided by the coils in the two circuits.
		The two tuned circuits are coupled together illustratively by transformer 44, the current in circuit 41 being in phase with the voltage across the capacitor in circuit 42 in accordance with well-understood principles.
		In such a case, the refresh pulses may be referenced, for example, to either zero current or zero voltage crossings preferably in the coil of the parallel tuned circuit.
	xrint.com /patents/us/3934235 (3360 words)

	Signal priority logic for serial printer - United States Patent 4,035,781
		Appropriate and conventional linkage and mounted means (not shown) coupled between the lever 40 and the platen 16 achieves the desired shifting of the platen in response to movement of the lever 40.
		Output circuitry is coupled to the rotor winding for deriving four positions signals, each of which is triangular in configuration during rotation of the rotor and thus print wheel wherein a first pair of the position signals are 90.degree.
		Due to the specific logic configuration utilized, particularly the operation of flip-flops 228 and 230, the occurrence of an unwanted counting pulse during a return from an overshoot condition is inhibited.
	xrint.com /patents/us/4035781 (17628 words)

	Optically coupled differential data link - Patent 4569059
		Referenced to the transmission lines, a logic "1" corresponds to current flow on the data lines in the direction shown on FIG.
		The procedure for transmission of a logic "0" is identical to the above described operation, except that the input drive conditions at the transmitter circuits are reversed.
		For the case of a logic "0" LD (-) is high thereby causing transistor Q4 to be "on." Current flows from the +5 V supply through Q4 and resistor R9 onto the L (-) line.
	www.freepatentsonline.com /4569059.html (2826 words)

	United States Patent: 6,649,476 (Site not responding. Last check: 2007-11-04)
		The dynamic logic circuit further comprises logic circuitry, configured to define a logic function, coupled between a low voltage and the output configured to be precharged high.
		The static logic circuit further comprises logic circuitry, configured to define a logic function, coupled between a low voltage and the output configured to be precharged low.
		The outputs of the logic circuits are preset (precharged) high (for a pull-down circuit 24) or low (for a pull-up circuit 40), and hence the logic circuits either stay with that output value or switch to the other during evaluation.
	web.engr.oregonstate.edu /~flf/6649476.html (4657 words)

	Digital Electronics
		Emitter Coupled Logic - This is a general introduction to ECL technology.
		Usually in external interfaces the digital logic signal are converted with some interfacing IC to something suitable in the transmitting end and back to normal logic signal on the receiving end.
		One of those discarded ideas was to move beyond binary logic to circuits based on multi-valued logic in which the information density and processing efficiency of a circuit could theoretically be increased substantially without any further expensive "improvements" to the underlying fabrication technology.
	www.epanorama.net /links/digital.html (4766 words)

	High Performance Computing and Communications Glossary (Site not responding. Last check: 2007-11-04)
		A form of parallelism exploited by some implementations of parallel logic programming languages, in which the terms in conjunctions are evaluated simultaneously, and parent computations are allowed to proceed only once their immediate children have completed.
		In small computer systems where all components can be synchronized, clock time and logical time may be the same everywhere, but in large systems it may be difficult for a processor to correlate the events it sees with the clock time an external observer would see.
		A form of parallelism exploited by some implementations of parallel logic programming languages, in which the terms in disjunctions are evaluated simultaneously, and the parent computation allowed to proceed as soon as any of its children have completed.
	www.cs.ualberta.ca /~paullu/C681/hpccgloss.html (13558 words)

	Analog Devices: D/Aコンバータ: Tutorial MT-009: Data Converter Codes—Can You Decode Them?
		Information in digital form is normally represented by arbitrarily fixed voltage levels referred to "ground," either occurring at the outputs of logic gates, or applied to their inputs.
		Words are groups of levels representing digital numbers; the levels may appear simultaneously in parallel, on a bus or groups of gate inputs or outputs, serially (or in a time sequence) on a single line, or as a sequence of parallel bytes (i.e., "byte-serial") or nibbles (small bytes).
		For example, a 16-bit word may occupy the 16 bits of a 16-bit bus, or it may be divided into two sequential bytes for an 8-bit bus, or four 4-bit nibbles for a 4-bit bus.
	www.analog.com /jp/content/0,2886,761__91285,00.html (2806 words)

	PECL LVPECL and ECL Clock Oscillators - ECL and PECL Crystal Oscillators - Positive-Referenced Emitter-Coupled Logic
		PECL LVPECL and ECL Clock Oscillators - ECL and PECL Crystal Oscillators - Positive-Referenced Emitter-Coupled Logic
		manufactures high quality Positive-referenced Emitter-Coupled Logic (pecl) Oscillators.
		FMI also offers ECL Oscillators or Emitter-Coupled Logic Oscillators.
	www.frequencymanagement.com /peclxos.html (33 words)

	App Note Abstract: Interfacing Between LVPECL, LVDS, and CML
		This application note describes various methods of interfacing between different logic levels.
		It focuses on interconection between LVPECL (low voltage positive-referenced emitter coupled logic), CML (current mode logic), and LVDS (low voltage differential signals).
		Although there are various methods to interconnect between these signal levels, this report mainly focuses on three interfaces: LVPECL to LVPECL, LVPECL to CML, and LVDS to LVDS.
	www.ti.com /sc/docs/psheets/abstract/apps/scaa056.htm (79 words)

	Sci.electronics FAQ
		Most video equipment are AC coupled (at least the input), which is the reason why you can't get away without fl level clamping if you plan to process the video signal.
		You use open-collector logic and thus the ouput is simply the collector of the transistor for each simple gate.
		The logic I had you use is called open collector DTL logic, and it was used in the early 70's both on chips and out of discrete components.
	www.ee.washington.edu /circuit_archive/circuits/F_ASCII_Schem_PC.html (2724 words)

	LVDS, CML, ECL-differential interfaces with odd voltages
		ECL - Emitter Coupled Logic - is the oldest of the three and dates back to the early 1960s.
		The drivers are low impedance open emitter outputs that generate a typical 700 to 800 mV output voltage.
		PECL - Positive Emitter Coupled Logic, also sometime referred to as Pseudo ECL is really just operating the ECL devices between and positive voltage and ground, vs ground and a negative voltage.
	www.national.com /nationaledge/may03/article.html (2970 words)

	NEL Frequency Controls, Inc.
		PECL devices need to have this addressed aggressively, since PECL is referenced only to the most positive side of the power supply.
		Given this range and the output drive capability of the emitter followers, the termination resistor can also serve the purpose of the pull-down resistor, but in several termination schemes, they are indeed kept as separate components.
		The primary steps to success are to utilize a PECL differential output logic clock oscillator that provides fast signal transitions; a PECL differential clock driver; dedicated PECL-to-CMOS translators for each load point; and impedance matched and properly terminated transmission lines.
	www.nelfc.com /white_meth.html (1377 words)

	TTL COMPATIBLE INPUT FOR BIMOS CIRCUITS
		Some technologies such as Power SIMOS which combine bipolar and MOS devices do not allow the bipolar devices to be referenced to ground, thereby making it difficult to achieve the TTL input voltage.
		This restriction is the result of a P type substrate serving as the output of the circuit, thereby limiting all epitaxial regions (PNP bases and NPN collectors) to a voltage level at or near the positive supply voltage.
		A lower collector potential may result in a parasitic four layer latch (substrate, epitaxial, base, emitter) in those technologies using the substrate as the output.
	www.priorartdatabase.com /IPCOM/000005556 (386 words)

	New World Vistas Air and Space Power for the 21st Century Summary Volume
		It was the evolutionary development of the thermonuclear weapon from the fission weapon coupled with the evolution of the ICBM from the V-2 that produced the profound effects on society.
		The folly of that logic was recognized millions of years ago in biological evolution, because the absence of biological diversity in a species makes the entire species susceptible to a single virus.
		The long baseline will make precise location of the emitter possible.36 We have discussed the use of commercial imaging for mapping [37] and the use of commercial constellations for providing communication services for onboard military hyperspectral systems.[38] Those discussions will not be repeated here.
	www.au.af.mil /au/awc/awcgate/vistas/vistas.htm (20881 words)

	Emitter Coupled Logic (Site not responding. Last check: 2007-11-04)
		External links [http://www.play-hookey.com/digital/electronics/ecl_gates.html logic* levels to the differential amplifier, so that the appropriate logical transistors to steer current through gates which compute logical functions (as significantly on the state of the circuit.
		The fact that the high and low logic levels are function of the input voltages will control the amplifier and the base of the Emitter-Coupled Logic] [http://www.wps.com/archives/solid-state- does every logic* family).
		Chip Design Magazine - A pioneer of Positive Emitter Coupled Logic (PECL) signaling, ON Semiconductor's latest family of PLL ICs offers performance compatible to the most widely used crystal oscillators at a fraction of the cost.
	doppler.boekebeurs.be /Emittercoupledlogic/Emitter-coupled-logic-.php (759 words)

	Fundamentals of Hardware Organization
		This circuit is thus an inverter, converting a logical 0 to a logical 1, and a logical 1 to a logical 0.
		The general idea is that when a word is referenced, it is brought from the large slow memory into the cache, so that the next time it is used, it can be accessed quickly.
		When a positive voltage is applied to the grid, the electrons are accelerated, causing the beam to hit the screen and make it glow briefly.
	www.cs.wayne.edu /~tom/guide/hw.html (5928 words)

	[No title]
		For high-speed clock and data systems, positive emitter-coupled-logic (PECL) - a differential signaling scheme - is emerging as a preferred alternative to single-ended CMOS and TTL logic.
		This is done in LVDS by adding a current source and resistor in each emitter circuit of the voltage follower.
		The emitter current is then adjusted so that the impedance seen looking into the output will be 50 ohm.
	www.planetanalog.com /showArticle.jhtml?articleID=164903593 (777 words)

	Various Schematics and Diagrams
		For a single output not referenced to a common, it doesn't matter whether a positive voltage regulator (as shown) or negative voltage regulator is used.
		The arc will be sustained with the filaments hot on an input as low as about 3.5 to 4 V (with a new tube) but during starting, an input voltage of about 5 or 6 V may be needed until the filaments are hot enough to sustain the arc at the lower voltage.
		This circuit (referenced in the document: Notes on the Troubleshooting and Repair of Electronic Flash Units and Strobe Lights and Design Guidelines, Useful Circuits, and Schematics is designed to provide a variety of options in terms of repetition rate, flash intensity, and various repeat and triggering modes.
	members.misty.com /don/samschem.htm (15414 words)

	PRL FAQs: ECL and PECL: Answers 1-4
		The basic circuit configuration consists of a pair of NPN transistors with their emitters connected together and fed by a current source as show in Fig.
		Note that the output emitters are open, and, unlike TTL/CMOS circuits, there will be no output until a pull-down resistor is connected to the open emitter.
		It should be pointed out that these logic levels are affected some what by the loading conditions.
	www.pulseresearchlab.com /faqs/ecl_ques/ecl_Q1-Q4.htm (750 words)

	Lightwave - VCSEL-based transmitters for parallel data communications
		A characteristic of multitransverse-mode VCSELs is the reduced speckle contrast in multimode fibers and therefore the reduced modal noise due to connector misalignment.
		If parallel fiber ribbons with MT receptacle transceivers are used, light can directly be coupled into an MT ferrule at low cost.
		Their electrical high-speed interfaces are compatible with low-voltage differential signal (LVDS), current mode logic, and positive-referenced emitter-coupled logic (PECL) standards and allow both AC and DC coupling.
	lw.pennnet.com /Articles/Article_Display.cfm?Section=Archives&Subsection=Display&ARTICLE_ID=94183&KEYWORD=vcsels (1725 words)

	HFAN-01.0: Introduction to LVDS, PECL, and CML - Maxim/Dallas
		Abstract: As the demand for high-speed data transmission grows, the interface between high-speed ICs becomes critical in achieving high performance, low power, and good noise immunity.
		Three commonly used interfaces are PECL (positive-referenced emitter-coupled logic), LVDS (low-voltage differential signals), and CML (current mode logic).
		When designing high-speed systems, people often encounter the problem of how to connect different ICs with different interfaces.
	www.maxim-ic.com /appnotes.cfm/appnote_number/291/ln/en (217 words)

	Electronic circuit design, PCB layout, system engineering - San Diego - Cornerstone Lab - Resume, HTML
		Designed a card that simulated an application specific integrated circuit (ASIC) for a contactless smart card with an embedded chip and antenna that communicates via radio frequency with special readers at the point of entry into transit fare gates, ticket vending machines (AVM), parking systems, and potentially, building doors and airport boarding gates.
		Featuring generic array logic (GAL) and discrete logic components; design of a custom carrying case/enclosure with power supply, internal and external cabling.
		Including a programmable logic controlled 28-lamp system activity monitor featuring high voltage current sensing, lamp life timer, lamp failure alarms, and AC to DC power supply.
	www.c-lab.com /resumeHTML.html (2720 words)

	Wireless Design & Development
		Integration of global positioning system (GPS) functionality into a growing number of portable devices — including GSM handsets — is driving the demand for small, low-power TCXOs that perform toward the top end of the stability scale.
		Differential outputs such as positive-referenced emitter-coupled logic (PECL) and low-voltage differential signaling (LVDS) are increasingly specified, as they offer sharp rise and fall times and so help to reduce data corruption.
		Across the communications industry, increasingly varied and sophisticated systems are being developed to deal with multiple protocols and data types.
	www.wirelessdesignmag.com /PRArchivebyIssue.aspx?RELTYPE=TF&YEAR=2006&MONTH=05 (1060 words)

	PCB design tool enables post layout analysis of signal integrity at up to Gigabit speeds
		CADSTAR SI Verify enables Fast Fourier Transform (FFT) analysis in time or frequency domains and provides sophisticated crosstalk analysis and optimization of track spacing.
		It also provides for simulation of differential pairs or positive-referenced emitter-coupled logic (PECL) and a parameter sweep helps determine the ideal values of passive components or transmission line lengths to achieve the desired electrical performance of nets.
		The tool is fully integrated into the CADSTAR design flow and engineers need not be signal integrity experts to be able use it.
	www.zuken.com /news/press0403cadstar-si-verify.asp (531 words)

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