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Topic: Processor architecture


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X86

In the News (Tue 23 Apr 19)

  
  Simulation/evaluation environment for a VLIW processor architecture
Processors capable of exploiting ILP contain multiple functional units, fetch several instructions per cycle from the instruction cache, and in a given cycle may dispatch multiple operations for execution.
The processor and memory models have a clearly defined interface, allowing a variety of models to be used interchangeably, with the models differing both in the system configuration they implement and in the degree of detail and accuracy involved.
Since a VLIW processor is characterized by having many functional units, the execution of an instruction pair as two separate instructions might not be detrimental as long as the pair is not in the critical path of the program (neglecting penalties arising from having larger code size).
www.research.ibm.com /journal/rd/413/moreno.html   (8020 words)

  
 Embedded.com - Network Processor Programming   (Site not responding. Last check: 2007-10-13)
A network processor is used in a network traffic manager, which occupies the space between a network interface and a switch fabric in a switcher/router.
The pipeline architecture is difficult to load balance because the rate of progress of the entire pipeline is determined by the slowest stage.
Some network processor vendors consider C++ language support unimportant given the small quantity of code that runs on the PE and the architectural sacrifices that would have to be made to conform to a C++ programmer's model.
www.embedded.com /story/OEG20010730S0053   (5115 words)

  
 [No title]
The Cell processor consists of a general-purpose POWERPC processor core connected to eight special-purpose DSP cores.
However, moving core processor functionality into software meant moving it into main memory, and this move put Transmeta's designs on the wrong side of the ever-widening latency gap between the execution units and RAM.
What I've tried to illustrate with this diagram and the preceding ones is that there is a homology between the growth of on-die control logic that intervenes between the cache and the execution core and the growth of memory latency.
arstechnica.com /articles/paedia/cpu/cell-1.ars   (1117 words)

  
 ARM architecture - Wikipedia, the free encyclopedia
The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture that is widely used in a number of embedded designs.
The ARM processor also has some features rarely seen on other architectures that are considered RISC, such as PC-relative addressing (indeed, on the ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.
ARM has implemented a technology that allows certain of their architectures to execute Java bytecode natively in hardware, as another execution mode.
en.wikipedia.org /wiki/ARM_architecture   (2477 words)

  
 Analog Devices : Embedded Processing & DSP : Blackfin : Overview : Blackfin Processor Architecture Overview
Blackfin Processors are a new breed of 16-32-bit embedded processor designed specifically to meet the computational demands and power constraints of today's embedded audio, video and communications applications.
The Blackfin Processor architecture is based upon a 10-stage RISC MCU/DSP pipeline with a mixed 16-/32-bit Instruction Set Architecture designed for optimal code density.
Blackfin processors architecture is also fully SIMD compliant and includes instructions for accelerated video and image processing.
www.analog.com /processors/blackfin/overview/archOverview.html   (1192 words)

  
 IBM JRD 49-4/5 | Introduction to the Cell multiprocessor
The Broadband Processor Architecture [10] is intended to have a life well beyond its first incarnation in the first-generation Cell processor.
While the processor matches the 11 FO4 design frequency of the SPEs on a fully compliant Power processor, its pipeline depth is only 23 stages, significantly less than what one might expect for a design that reduces the amount of time per stage by nearly a factor of 2 compared with earlier designs [12, 13].
With the architectural improvements that remove the latency-induced limitation on bandwidth, the next challenge is to make significant improvements in delivering bandwidth to main memory and bandwidth between the processing elements and interfaces within the Cell processor.
www.research.ibm.com /journal/rd/494/kahle.html   (7947 words)

  
 Coarse-Grain Reconfigurable Processor Architecture
ADRES (Architecture for Dynamically Reconfigurable Embedded System) is a flexible architecture template that consists of a tightly coupled VLIW (Very Long Instruction Word) processor and a coarse-grained reconfigurable array.
In addition, the coarse-grained reconfigurable architecture consists of components which are similar to those used in VLIW processors.
The VLIW processor consists of several FUs and a multi-port register file, as in typical VLIW architectures, but in this case the VLIW is also used as the first row of the reconfigurable array.
www.imec.be /reconfigurable/architecture.shtml   (589 words)

  
 CPU design - Wikipedia, the free encyclopedia
The Burroughs architecture was one of the inspirations for Charles H. Moore's Forth language, which placed six 5-bit instructions in a 32-bit word.
In older processor designs, now retroactively known as CISC, the instructions were offered in a number of different modes that meant that step 2 took an unknown length of time to complete.
In multithreading, when the processor has to fetch data from slow system memory, instead of stalling for the data to arrive, the processor switches to another program or program thread which is ready to execute.
en.wikipedia.org /wiki/Processor_architecture   (7078 words)

  
 CoWare Processor Designer Technical Overview
The Processor Designer product family is ideal for embedded processor designers, SoC designers, using commercial processor IP from 3rd party vendors, and those designing custom non-standard processors integrated into SoCs.
Design of new architectures requires designers to work in two fields: hardware development of the processor architecture and software toolchain development for the compiler, assembler, linker, simulator and debugger.
Most of today's processor design is done using a variety of development tools from different sources, typically lacking a high quality, tightly integrated and unified approach.
www.coware.com /products/processordesigner_tech.php   (848 words)

  
 [No title]
Instructions make their way from the cache to the front end and down through the execution engine, which is where the actual work of number crunching gets done.
While most processors do have one-cycle instructions (the P4 even has 0.5-cycle instructions), they also have some really complicated instructions that need to spend multiple cycles in the EXECUTE stage.
The take-home message here is that when we talk about how many pipeline stages a processor has we use an ideal number that pretends that each instruction spends only one cycle in the EXECUTE stage, but most instructions pass through multiple EXECUTE stages in the various functional units.
arstechnica.com /articles/paedia/cpu/p4andg4e.ars/1   (934 words)

  
 Processor Architecture Patterns
One of the most important steps in architecture design is identifying processors/modules in the system and assigning roles/requirements to them.
When you are designing a distributed system the operations and maintenance processor should provide a unified view about the management of the system.
If a IP based architecture is used, the central manager and the highest level module managers should communicate on a single IP network.
www.eventhelix.com /RealtimeMantra/Patterns/processor_architecture_patterns.htm   (1540 words)

  
 Cray Inc - The Supercomputer Company > Products > XD1 > DCP Architecture   (Site not responding. Last check: 2007-10-13)
Cray’s Direct Connected Processor (DCP) architecture addresses these limitations by fusing the processor directly to the interconnect fabric, eliminating memory contention and PCI bus bottlenecks.
Systems using the memory connected processor architecture are those where interprocessor communications takes place through a shared memory.
The directed connected processors architecture applies to systems where processors are tied directly into a message passing, switched interconnect.
www.cray.com /products/xd1/architecture.html   (462 words)

  
 Cell Broadband Engine Architecture from 20,000 feet
While each SPE is an independent processor running its own application programs, a shared, coherent memory and a rich set of DMA commands provide for seamless and efficient communications between all Cell processing elements.
The second type of processor, the SPE, is optimized for running compute-intensive applications, and it is not optimized for running an operating system.
Peter Hofstee is the chief architect of the Cell Synergistic Processor, and Cell chief scientist.
www-128.ibm.com /developerworks/power/library/pa-cbea.html   (1341 words)

  
 A Minimal TTL Processor for Architecture Exploration
The PISC is a processor constructed from discrete TTL logic, which illustrates the operation of both hardwired and microcoded CPUs.
An educational drawback of the PISC is its abysmal implementation of "conventional" (1- or 2-operand) macromachines.
This is a consequence of the PISC's original "mission": a stack processor using a minimum of standard TTL logic (2100 gates).
www.zetetics.com /bj/papers/piscedu2.htm   (2083 words)

  
 Tensilica - Xtensa LX Architecture
The base architecture has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special purpose registers and 80 base instructions, including compact 16- and 24-bit (rather than 32-bit) RISC instruction encoding.
The Xtensa LX2 processor implements the proven Xtensa instruction set architecture (ISA), which enables designers to achieve significant code size reductions compared to conventional RISC cores.
The FLIX architecture allows the implementation of highly parallel processors with a performance characteristic of specialty ultra-wide instruction word processors, without the negative code size implications typically found in such VLIW or ULIW solutions.
www.tensilica.com /products/lx_architecture.htm   (450 words)

  
 Processor Architecture helps develop consumer devices., LSI Logic Corp.
Dubbed ZEVIO(TM), the application processor architecture is ideally suited for consumer electronics products such as GPS navigation systems, electronic toys and edutainment applications, personal media players, and handheld products.
The ZEVIO architecture is being announced and demonstrated during the Consumer Electronics Show in Las Vegas, Central Hall Booth #15044.
Aug 2, 2006 - Audio Processors combine DSP with digital and analog I/O. May 8, 2006 - Mobile Phone Processor is fully HSDPA compliant.
news.thomasnet.com /fullstory/476065/rss/264   (1304 words)

  
 IBM Research | IBM Research | The Cell architecture   (Site not responding. Last check: 2007-10-13)
Cell is a heterogeneous chip multiprocessor that consists of an IBM 64-bit Power Architecture™ core, augmented with eight specialized co-processors based on a novel single-instruction multiple-data (SIMD) architecture called Synergistic Processor Unit (SPU), which is for data-intensive processing, like that found in cryptography, media and scientific applications.
While the SPU ISA is a novel architecture, the operations selected for the SPU are closely aligned with the functionality of the Power™ VMX unit.
During the course of this partnership with the STI Design Center, members of the original Cell team developed the first SPU compiler, which was a guiding force for the definition of the SPU architecture and the SPU programming environment, and sample code to exploit the strengths of the broadband processor architecture.
domino.research.ibm.com /comm/research.nsf/pages/r.arch.innovation.html   (1819 words)

  
 Counterflow Pipeline Processor Architecture
The counterflow pipeline processor architecture (CFPP) is a proposal for a family of microarchitectures for RISC processors.
The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass.
The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs.
research.sun.com /techrep/1994/abstract-25.html   (185 words)

  
 Diamond Standard Processors Architecture
Tensilica’s Diamond Standard processors are based on Tensilica's proven Xtensa architecture, which is used across a wide range of electronic products, from low-cost portable consumer applications to carrier-class networking routers.
This architecture is extended with 64-bit VLIW (very long instruction word) “bundles” – which are composed of multiple instructions - for the Diamond 570T, 330HiFi and 545CK processors.
The Diamond Standard Series processor architecture dramatically lowers power consumption since it is designed to use power very efficiently.
www.tensilica.com /diamond/di_architecture.htm   (903 words)

  
 Evolution of the multi-core processor architecture Intel Core: Conroe, Kentsfiel
I hope our readers, after "digesting" the architectural features of Intel's new generation of processors, will be able not only scrutinizing the "marks" in a laid-back way, but also get a better idea of the causes and consequences which lead to a specific result.
The most precise, authentic and detailed information on the inner structure of Intel's new-generation processors for desktop PCs which are expected to emerge in the nearest future was made public during the spring forums arranged by Intel for developers - Intel Developer Forum, and during the Moscow IDF Spring 2006, in particular.
The new processor architecture inherits the philosophy of effective power consumption first implemented in Intel Pentium M processors for mobile PCs having the working name Banias.
www.digital-daily.com /cpu/new_core_conroe   (1430 words)

  
 What is SPARC? - a definition from Whatis.com - see also: Scalable Processor Architecture
SPARC (Scalable Processor Architecture) is a 32- and 64-bit microprocessor architecture from Sun Microsystems that is based on reduced instruction set computing (RISC).
Although the idea of RISC is sometimes attributed to IBM's John Cocke, Sun Microsystems was the first to provide a microprocessor that exploited it for the workstation market and it's possible to say that, together with Unix, SPARC created the workstation market.
Reduce the number of instructions that the processor has to perform to a minimal number (one idea of RISC is that a complex instruction in a conventional computer can be reduced to a series of simpler operations, requiring a simpler architecture and a more compact microprocessor)
whatis.techtarget.com /definition/0,,sid9_gci213701,00.html   (377 words)

  
 IBM Tips Power6 Processor Architecture - Hardware News by InformationWeek   (Site not responding. Last check: 2007-10-13)
It's a 65-nm processor that operates in excess of 4-GHz.
In various papers at the event, IBM indicated that the Power6 is a 65-nm processor that operates in excess of 4-GHz.
The processor is said to have an eight-way, set-associative design with a two-stage pipeline supporting two independent reads or one writes per cycle.
www.informationweek.com /hardware/showArticle.jhtml?articleID=179100699   (286 words)

  
 Processor Architecture Laboratory
The performance of the processor memory subsystem (the system that mainly consists of Memory Management Unit, or MMU, caches and the main memory) and its performance plays a crucial role in the performance of the overall computer system.
In this project you will be able to play with the vhdl-source set of a widely used three-stage pipelined industrial processor, learn the in and outs of a real processor architecture, and experience the difficulties verifying and validating the correctness of a real processor.
As the current C-based simulation model of the URLAP processor only runs at an equivalent clock frequency of 100kHz on a P4 3.6GHz machine, it is not very suitable for multi-processor simulations (as the equivalent processor clock frequency scales down with the number of processors involved).
diwww.epfl.ch /lap/projects/database/list.php   (3669 words)

  
 EETimes.com - AMD shows 64-bit processor architecture
While analysts give some weight to this argument, AMD counters by stating that its own architecture is backwards-compatible with all existing systems and software, and will be much easier for engineers to design into products.
With AMD only now releasing the architectural details of its X86-64 design, Mitton said there will be samples of its first implementation, the Sledgehammer, sometime next year, and volume production is expected in 2002.
The current crop of 32-bit processors can only address up to 4 Gbytes of system memory, and that's a limiting factor for today's high-end servers and systems that power major databases.
www.eetimes.com /story/OEG20000810S0035   (999 words)

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