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Topic: Programmable Interrupt Controller

	PIC - Personal Information Carrier, Personal Intelligent Communicator, Point In Call, Primary Interexchange Carrier, ...
		The PIC code is configured as a prefix to the dialed number.
		A PIC is the long distance company that the user wants to handle his or her 1+ calls.
		An abbreviation for "pass investment tax credit." A PIC lease is one in which the lessor passes the investment tax credit through to the lessee.
	www.auditmypc.com /acronym/PIC.asp (560 words)

	Programmable interrupt controller - Patent 5101497
		The interrupt controller I is attached to the central processor as an input/output peripheral.
		Control logic circuit 18 is the logic circuit which controls the transmittal of interrupt requests to the processor via the interrupt line (INT) and receives interrupt acknowledge signals from the processor via the interrupt acknowledge line (INTA).
		Interrupt controller I recognizes this command and in response thereto initiates an automatic sequence of operations on the various registers of the controller I utilizing data obtained via bus/buffer 16.
	www.freepatentsonline.com /5101497.html (4517 words)

	Programable interrupt controller - Patent 5261107
		The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis.
		A programmable interrupt controller in accordance with the invention advantageously provides flexibility in designing and implementing computer systems in that peripheral devices utilizing either edge-triggered or level-triggered interrupt requests may be used on the various interrupt request inputs.
		PIC ENABLE 158 is inverted by an inverter 160 to produce a PIC ENABLE signal 162 which is used where an active low signal indicating that the programmable interrupt controller is enabled is required.
	www.freepatentsonline.com /5261107.html (9754 words)

	Eureka Technology - Interrupt Controller IP core
		When there are multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority based on the interrupt levels and interrupt numbers of the sources.
		If the interrupt levels of the sources are different, the interrupt with higher level has priority.
		The cause of the interrupt that is being reported and the interrupt level are also reported.
	www.eurekatech.com /products/peripheral/ep610.htm (201 words)

	Key Benefits of the I/O APIC
		Interrupts have been most commonly handled using the same basic methodology as that used by the original PC-AT architecture--in other words, using legacy "chained" 8259 Programmable Interrupt Controller (PIC) devices.
		Whenever the interrupt signal is held low (for active-low interrupts, which are the most common), the interrupt controller will generate an interrupt.
		The PIC interrupt controller has a built-in hardware priority scheme that is not appropriate for machines running operating systems based on Windows NT Technology.
	www.microsoft.com /whdc/system/sysperf/IO-APIC.mspx (1846 words)

	[No title]
		Some of the interrupts in the system may be hard-wired, for example, the real time clock's interval timer may be permanently connected to pin 3 on the interrupt controller.
		The interrupt pin that an ISA device uses is often set using jumpers on the hardware device and fixed in the device driver.
		The interrupt pin that a device uses is fixed and is kept in a field in the PCI configuration header for this device.
	www.tldp.org /LDP/tlk/dd/interrupts.html (2180 words)

	CHAPTER SEVENTEEN: INTERRUPTS, TRAPS AND EXEPTIONS (Part 3)
		Hardware interrupts are the form most engineers (as opposed to PC programmers) associate with the term interrupt.
		If you do not send the end of interrupt command, the PIC will not honor any more interrupts from that device; if you send two or more end of interrupt commands, there is the possibility that you will accidentally acknowledge a new interrupt that may be pending and you will lose that interrupt.
		The 8250 (or compatible) serial communications controller chip (SCC) generates an interrupt in one of four situations: a character arriving over the serial line, the SCC finishes the transmission of a character and is requesting another, an error occurs, or a status change occurs.
	www.arl.wustl.edu /~lockwood/class/cs306/books/artofasm/Chapter_17/CH17-3.html (2478 words)

	Computer Science 314 - 8259 Interrupt Controller
		Control is transferred back to the interrupted task once the service routine has completed its task.
		Today, most PCs contain two interrupt controllers, with the secondary controller chained (cascaded) unto the first controller (on most PCs, the secondary controller is chained to the second interrupt line of the primary controller) making it unavailable to other devices.
		Upon receiving the EOI signal, the PIC clears the bit in the in-service register associated with interrupt 3 and is ready to accept new interrupts.
	www.cs.sun.ac.za /~lraitt/doc_8259.html (1612 words)

	Programmable Interrupt Controller - English Dictionary
		PIC A special-purpose integrated circuit that functions as an overall manager in an interrupt driven system.
		It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest priority, ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.
		PICs typically have eight interrupt lines, and two PICs are often cascaded to provide 15 available interrupt lines.
	www.english-dictionary.us /meaning/programmable_interrupt_controller.asp (87 words)

	The Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs
		The traditional 8259 interrupt controller is subject to significant legacy issues.
		Interrupt sharing has been required on many PC platforms, but it must be viewed as a necessary evil.
		These problems of interrupt latency, are, of course, not the only issues in today's machines that have to be addressed before real-time behavior can be convincingly achieved.
	www.microsoft.com /whdc/system/sysperf/apic.mspx (2928 words)

	Advanced Programmable Interrupt Controller (Site not responding. Last check: 2007-10-21)
		An IRQ-type interrupt routine wishes to wake a sleeping thread, but this IRQ interrupt may be nested several levels inside other IRQ interrupts, so it cannot simply switch stacks as those outer interrupt routines would not complete until the old thread is re-woken.
		Then, when all IRQ-type interrupt handlers have returned out, the LAPIC is now able to interrupt.It interrupts out of the currently executing thread and switches to the thread that was just woken.
		The quantum timer interrupt handler is very similar to the regular softint handler, except it decrements the current thread's priority.
	osdev.berlios.de /pic.xml (3376 words)

	What is an IRQ ? 8-bit Programmable Interrupt Controller IRQ
		The interrupt request signals run along the IRQ lines to an interrupt controller that assigns priorities to incoming IRQs and delivers them to the CPU.
		Since the interrupt controller expects signals from only one device per IRQ line, if you have more than one device sending IRQ signals along the same line, you get an IRQ conflict that can lock your system.
		The INT signal (Interrupt--prioritized interrupt) of the second 8259 was connected to the old IRQ2 pin on the first 8259 and the IRQ 2 line was plugged into IRQ 9 on the new 8259.
	bugclub.org /beginners/windows/IRQ.html (347 words)

	Interfacing The PC : Using Interrupts
		Most Ports/UARTs may interrupt the processor for a range of reasons, eg byte received, time-outs, FIFO buffer empty, overruns etc, thus the nature of the interrupt has to be determined.
		Before we can return from the interrupt, we must tell the Programmable Interrupt Controller, that we are ending the interrupt by sending an EOI (End of Interrupt 0x10) to it.
		The CPU only has one interrupt line, thus the second controller had to be connected to the first controller, in a master/slave configuration.
	www.beyondlogic.org /interrupts/interupt.htm (3111 words)

	Programmable Interrupt Controller
		A Programmable Interrupt Controller (or PIC) is an Intel 8259A chip that controls interrupts.
		Starting with the 286-based AT, there are two PICs in a personal computer, providing a total of 15 usable IRQs.
		The PIC has been superseded by an Advanced Programmable Interrupt Controller (APIC), or 82489DX chip, that is enhanced for multiprocessing.
	www.mrsci.com /Digital-Electronics/Programmable_Interrupt_Controller.php (74 words)

	The Definitive BIOS Optimization Guide
		The I/O APIC is the replacement for the old chained 8259 PIC (Programmable Interrupt Controller) still in use in many motherboards.
		It collects interrupt signals from I/O devices and send messages to the local APICs via the APIC bus which connects it to the local APICs.
		To sum it all up, APIC provides multiprocessor support, more IRQs and faster interrupt handling which are not possible with the old 8259 PIC.
	www.adriansrojakpot.com /Speed_Demonz/New_BIOS_Guide/APIC_Function.htm (465 words)

	8259 Programmable Interrupt Controller (Site not responding. Last check: 2007-10-21)
		Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
		In slave mode, the PIC reads slave ID no. from master on these lines.
		In non-buffered mode, it is SP-bar input, used to distinguish master/slave PIC.
	www.thesatya.com /8259.html (292 words)

	8259 Programmable Interrupt Controller (Site not responding. Last check: 2007-10-21)
		Figure 1 shows the block diagram for the 8259 programmable interrupt controller (PIC) megafunction.
		The 8259 PIC is functionally based on the Intel 8259A.
		Eight interrupt requests are prioritized for a processor.
	www.altera.com /products/ip/iup/peripherals/m-inn-8259.html (88 words)

	Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) Datasheet
		The 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors.
		Each interrupt pin is individually programmable as either edge or level triggered.
		The interrupt vector and interrupt steering information can be specified per interrupt.
	www.intel.com /design/chipsets/datashts/290566.htm (118 words)

	HI-TECH Software Forums: the programmable interrupt controller. MSP vs. PIC
		Ironically, you are using PIC to mean Programmable Interrupt Controller, whereas PIC is also the prefix for Microchip part numbers — e.g., PIC12F6893.
		The INT output is an external interrupt for the ATMEL.
		When the AVR goes to sleep it should set W/R to 1 which means that the PIC drives CODE and D/C. Those lines are the direct connection between the ATMEL and the PIC.
	www.htsoft.com /forum/all/showflat.php?Number=15105&page=0 (1019 words)

	Tandon BIOS Post Codes
		8254 programmable interrupt timer test failed, xx is the failing channel number
		Install interrupt handler and vector for interrupt 0F to check for unexpected interrupts; Halt is unexpected interrupt occurs
		Unexpected interrupt did not occur; Test 8254 programmable interrupt timer channel 0, IRQ 0 and software interrupt 8 tests
	www.pantz.org /hardware/bios/tandonbios.htm (968 words)

	PearPC - About
		PIC: A programmable interrupt controller (kind of Heathrow).
		Network Controller: Emulates a 3COM 3C90x or RealTek 8139 via hosts that support an ethernet tunnel.
		Sufficient to make the client think that it has USB support.
	pearpc.sourceforge.net /about.html (319 words)

	Urban Legends Reference Pages: Keyboard Loggers
		On one side of the board, one Atmel AT45D041A four megabit Flash memory chip.
		On the other side, one Microchip Technology PIC16F876 Programmable Interrupt Controller, along with a little Fairchild Semiconductor CD4066BCM quad bilateral switch.
		Looking further, I saw that the other end of the cable was connected to the integrated ethernet board.
	www.snopes.com /computer/internet/dellbug.asp (397 words)

	Advanced Programmable Interrupt Controller Definition. Define Advanced Programmable Interrupt Controller. What is ...
		How Do I Create a Network of People?
		Free Definitions : Define Advanced Programmable Interrupt Controller.
		(APIC) A {Programmable Interrupt Controller} (PIC) that can handle {interrupts} from and for multiple {CPU}s, and, usually, has more available interrupt lines that a typical PIC.
	www.learnthat.com /define/hitting.asp?ID=1331 (103 words)

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