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Topic: Programmable logic device

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Programmable Logic Array

Digital logic

Logic gate

Hardware description language

ABEL programming language

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	Logic gate - Encyclopedia.WorldSearch (Site not responding. Last check: 2007-11-06)
		Logic circuits are often classified in two groups: combinatorial logic, in which the outputs are continuous-time functions of the inputs, and sequential logic, in which the outputs depend on information stored by the circuit as well as on the inputs.
		Increasingly, these fixed-function logic gates are being replaced by programmable logic devices, which allow designers to pack a huge number of mixed logic gates into a single integrated circuit.
		The field programmable nature of programmable logic devices such as FPGAs has removed the 'hard' property of hardware, it is now possible to change the logic design of a hardware system by reprogramming some of its components thus allowing the features or function of a hardware implementation of a logic system to be changed.
	encyclopedia.worldsearch.com /logic_gate.htm (1697 words)

	Programmable logic device - Wikipedia, the free encyclopedia
		A programmable logic device or PLD is an electronic component used to build digital circuits.
		An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor.
		A PLD is a combination of a logic device and a memory device.
	en.wikipedia.org /wiki/Programmable_logic_device (1293 words)

	Programmable logic device with versatile exclusive or architecture - US Patent 6069488 (Site not responding. Last check: 2007-11-06)
		A programmable logic device according to claim 3, further comprising a third OR gate having an input connected to the output of said first OR gate, said switching means being switchable to alternately connect the output of said third OR gate and the output of said EXCLUSIVE OR gate to said output line.
		The logical OR output 54 of the OR gate 51 is connected to the non-inverted and inverted inputs 61, 62 of multiplexer 60 while the XOR output 58 of the fixed XOR gate 55 is connected to the inverted and non-inverted inputs 63, 64 of the multiplexer 60.
		The logical output of the cell 10 is at the output 65 of multiplexer 60.
	www.patentstorm.us /patents/6069488.html (5057 words)

	A Tour of PLDs: Programmable Logic Device (PLD) Handout
		A programmable logic array is normally composed of a specific number of input lines connected through a fixed or programmable array to a set of AND gates, which are in turn connected to a fixed or programmable array of OR gates.
		Programmable inversion is provided between the PAL array and the flip-flop inputs, simplifying the use of programmable polarity.
		A programmable device that can't be erased and reprogrammed.
	www.eej.ulst.ac.uk /~ian/modules/EEE515J1/files/Tour_of_PLDs.htm (12123 words)

	Programmable Logic Overview - PLD, CPLD, FPGA
		Unlike the programmable interconnect within a PLD, the switch matrix within a CPLD may or may not be fully connected.
		The overall process of hardware development for programmable logic is shown in Figure 3 and described in the paragraphs that follow.
		Programmable logic devices are like non-volatile memories in that there are multiple underlying technologies.
	www.netrino.com /Articles/ProgrammableLogic (3556 words)

	Tutorial - Programmable Logic Device Definitions
		Programmable Logic - a logic element whose function is not restricted to a particular function.
		The device is programmed by turning on switches which make connections between circuit nodes and the metal routing tracks.
		The UTMC UT22VP10 device uses an amorphous silicon antifuse as the programmable element.
	klabs.org /richcontent/Tutorial/PLD_Definitions.htm (1027 words)

	FaQ
		A generic description of an FPGA is a programmable device with an internal array of logic blocks, surrounded by a ring of programmable input/output blocks, connected together via programmable interconnect.
		One successful technique for programmable logic design is to functionally simulate the design to guarantee proper functionality, verify the timing using a static timing calculator, and then verify complete functionality by testing the design in the system.
		All fuse- and anti-fuse-based devices are one-time programmable.
	www.geocities.com /abel_mutlu/faq1.htm (3560 words)

	Programmable logic device (EP0584911B1) (Site not responding. Last check: 2007-11-06)
		The programmable logic device (PLD) of this invention includes two or more programmable logic blocks (101-A-101H) interconnected by a programmable switch matrix that includes a programmable input switch matrix (120) (input switch matrix) and a programmable centralized switch matrix (130) (centralized switch matrix).
		The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix (140).
		further wherein said programmable centralized switch interconnection means (130) selectively connects and disconnects signals on said plurality of input lines of said programmable centralized switch interconnection means to said pluralities of input lines of said plurality of programmable logic blocks.
	www.delphion.com /details?&pn=EP00584911B1 (626 words)

	Kanda UK - CUPL PLD Programmable Logic Device programmers and logic training
		Atmel simple PLD (Programmable Logic Device) such as 16V8 and 22V10 are flash based programmable logic, so are re-programmable 100's of times.
		The 16V8 PLD is ideal for logic training and general electronics as it can be programmed to be logic gates, inverters, flip-flops and registers using the CUPL programmable logic description language.
		CUPL Programmable Logic Description Language is a compiler that converts logic equations into a Fuse map (JEDEC file) for the PLD programmer.
	www.kanda.com /cupl-pld-training.html (397 words)

	PLD - Programmable Logic Device (Site not responding. Last check: 2007-11-06)
		The group of devices known as PLDs include PROMs, Programmable Logic Arrays (PLA), and Programmable Array Logic/Generic Array Logic (PAL/GAL).
		SPLDs, CPLDs and FPGAs are classes of PLDs.
		(Programmable Logic Device) A digital IC that can be programmed by the user to perform a wide variety of logical operations.
	www.auditmypc.com /acronym/PLD.asp (173 words)

	Glossary
		FPGA (Field Programmable Gate Array) A class of integrated circuits pioneered by Xilinx for which the logic function is defined by the customer using development system software AFTER the IC has been manufactured and delivered to the end user.
		Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide.
		PLD (Programmable Logic Device) A digital IC that can be programmed by the user to perform a wide variety of logical operations.
	www.corporate-ir.net /media_files/nsd/xlnx/annual96/glossary.htm (524 words)

	Electronic News: Altera, Atmel heat up PLD markets - programmable logic device (Site not responding. Last check: 2007-11-06)
		The 10ns, 128-macrocell EPM7128E was cut 32 percent to $45.95 per unit; the 10ns, 160-macrocell EPM7160E was reduced 45 percent to $87.95; the 12ns, 192-macrocell EPM7192E was lowered 31 percent to $129.95; and the 12ns, 256-macrocell EPM7256E fell 18 percent to $199.95 each.
		Programmable logic is roughly $1 billion this most recent year, or roughly 8 percent.
		The AT6000 family has thousands of registers and XORs (and/or functions), as well as a means of implementing reconfigurable hardware using Cache Logic, a proprietary design technique developed to implement a broad range of applications in a single Atmel FPGA without loss of speed through the use of dynamic reconfiguration.
	www.findarticles.com /p/articles/mi_m0EKF/is_n2047_v41/ai_16674071 (978 words)

	[No title] (Site not responding. Last check: 2007-11-06)
		Validation 10 Purpose The purpose of this project is to design a sequence generator that produces a series of six-bit one-hot code words using the programmable logic device.
		The intention of this design project is to take the concepts of programmable design that we have acquired and test to see how the program would apply to the hardware.
		The programmable Logic device was very efficient device to use.
	filebox.vt.edu /s/sehan/Project4.doc (661 words)

	CS37 Programmable Logic Device Directions (Site not responding. Last check: 2007-11-06)
		Connect an I/O device (such as a binary switch) to the input of the buffer.
		Label the Buffer-4 "Btn0", and connect four I/O device signals (such as a hex keyboard or four binary switches) to the buffer input pins.
		Connect four I/O device signals (such as a hex keyboard or four binary switches) to the buffer input pins.
	www.cs.dartmouth.edu /~hawblitz/teach/cs37-03x/pld.html (1054 words)

	The Semiconductor Reporter
		The devices provide power-supply monitoring and sequencing control through in-system programmable analog and logic blocks, said the company, which is now making a play for a portion of the $12 billion power semiconductor market.
		Lattice said a combination of programmable logic, voltage comparators, references, and high-voltage FET drivers, provide a single-chip programmable power supply and monitoring capability.
		The device has been "ruggedized" to operate in noisy power supply environments from 2.25-to-5.5-volts and is packaged in a 44-pin thin quad flat pack (TQFP) package, said the Hillsboro company.
	www.semireporter.com /public/2162.cfm (229 words)

	(WO 01/39376) PROGRAMMABLE LOGIC DEVICE AND PROGRAMMING METHOD (Site not responding. Last check: 2007-11-06)
		(57) Before logic setting data for a programmable logic device (PLD) is transferred from a memory, pin setting data for defining the initial state of an external pin of the PLD is transferred to set all the external pins.
		The logic setting data is divided into minimum logic setting data for defining functions necessary for the stable operation of the system and complete logic setting data for defining all the functions including the other functions.
		The former data is preferentially transferred, and thereby the period during which the PLD is unstable at the system start-up, solving the unstability at the start-up when the device is assembled into an existing system.
	www.wipo.int /ipdl/IPDL-CIMAGES/view/pct/getbykey5?KEY=01/39376.010531 (257 words)

	[No title]
		Part II: Using Programmable Array Logic Device In this part, a PAL device is used in place of the 4-bit adder and combinational network.
		The second part showed that the same circuit could be implemented on a single PAL device, with the same results and minimal effort and time.
		Thus, the benefits of using PAL devices were successfully shown.
	wwwcsif.cs.ucdavis.edu /~wongak/180A/Lab5-180A.doc (189 words)

	NASA Survey on Programmable Logic
		Programmable Logic Controllers (PLCs) are solid-state members of the computer family, using integrated circuits instead of electromechanical devices to implement control functions.
		Programmable Logic devices are becoming common within NASA and in industry.
		This hybrid aspect of Programmable Logic may not be fully addressed when the devices are developed, tested, and verified.
	smad-ext.grc.nasa.gov /rmo/plcsurvey (482 words)

	BvR electronic Chooses Lattice Programmable Logic Device for Digital Display Link
		These devices are built around a new building block, the Multi-Function Block (MFB).
		This unparalleled PLD flexibility is combined with sysI/O™ interfaces for support of leading edge standards such as LVDS, HSTL, and SSTL, along with the more familiar LVCMOS standards.
		Devices are available to support 3.3, 2.5, and 1.8-volt power supply operation.
	www.latticesemi.com /corporate/press/product/2004/pr100704.cfm (871 words)

	SPLD/CPLD from Atmel (Site not responding. Last check: 2007-11-06)
		The ATF15xx CPLD family offers pin-compatible supersets of the popular Altera 7000 and 3000 series devices ranging from 32 to 128 (soon to be 256) macrocells with propagation delays from 7.5 to 15 ns for 5V standard power versions and 15 ns for 3.3V versions.
		More global clock pins, a programmable pin-keeper and the ability to realize two latches per macrocell are further examples of the enhanced features available from this CPLD product family.
		The ATF750C is ideal for those 22V10 designs that need a bit more logic than is offered in a 22V10 device, but need to maintain the 22V10 pin-out.
	www.atmel.com /atmel/products/prod2.htm (436 words)

	Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device (Site not responding. Last check: 2007-11-06)
		In this report we present a new architecture for a Field Programmable Logic Device.
		The central principle of the new architecture is based on the concept of efficient use of silicon resources.
		It is performance-oriented, with predictable interconnect and logic delays, and has a guaranteed routability.
	sunsite.berkeley.edu /TechRepPages/ERL-93-42 (281 words)

	Automatic generation of programmable logic device architectures (US6631510)
		The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of different architectures.
		The Architecture Generation Engine converts a high-level, easily specified description of a PLD architecture into the highly detailed, complete PLD architecture database required by the internals of the CAD toolset in order to map a circuit netlist into the PLD.
		The Architecture Generation Engine also enables the performance evaluation of a wide variety of PLD architectures for given benchmark circuits.
	www.delphion.com /details?&pn=US06631510__ (453 words)

	EDN: Determine PLD metastability to derive ample MTBFs. (Design Feature)(programmable logic device, mean time between ... (Site not responding. Last check: 2007-11-06)
		EDN: Determine PLD metastability to derive ample MTBFs.
		(Design Feature)(programmable logic device, mean time between failures)(includes related articles on physical characteristics of the test board and metastability basics) (tutorial)
		Determining the metastability characteristics of logic devices, especially programmable logic devices (PLDs), is a demanding task.
	www.highbeam.com /library/doc0.asp?DOCID=1G1:11124257&refid=holomed_1 (200 words)

	Programmable Logic Device (SPLDs & CPLDs) - Software (Site not responding. Last check: 2007-11-06)
		If you need a version with unlimited compiles or an upgrade, please contact Logical Devices.
		Device Library includes: ATF1508AS and ATF750C/CL in all available packages.
		An enable code will be automatically e-mailed to you so you can install the Device Kit.
	www.nalanda.nitc.ac.in /industry/datasheets/atmel/prod147.htm (521 words)

	SSS Online - Programmable Logic Device (PLD) Tools
		Programmable Logic Devices (PLDs) have not only become extremely popular, they now are the accepted norm in new logic designs.
		Programmable logic devices are hot these days - and there's a lot of tool offerings out there helping to make them happen.
		Verilog Simulation Bridges the Gap Between PLDs and ASICs, by Allen Vexler for ISD Magazine, August 1999.
	www.sss-mag.com /pldtools.html (308 words)

	FPGA Page (Site not responding. Last check: 2007-11-06)
		A discrete device can be used to implement a small amount of logic.
		A programmable device is a general-purpose device capable of implementing the logic of tens or hundreds of discrete devices.
		FPLDs can implement thousand of gates of logic in a single IC and it can be programmed by users at their site in a few seconds or less depending on the type device used.
	www.ele.auckland.ac.nz /archives/students/mche034/fpga.htm (306 words)

	Stretch Chip Embeds Programmable Logic Within the Processor - 5/1/2004 - ECN - CA415497 (Site not responding. Last check: 2007-11-06)
		Stretch, Inc. has announced the S5000 family of software-configurable processors that are designed to combine the best of general-purpose processors and the parallelism and flexibility of FPGAs.
		The ISEF is a software-configurable data-path based on proprietary programmable logic.
		The device addresses the data compute bandwidth bottlenecks by using thirty-two 128-bit-wide registers couple with 128-bit-wide access to memory to feed data to the ISEF at a high bandwidth.
	www.reed-electronics.com /ecnmag/article/CA415497?filename=ECN20040501... (277 words)

	[No title] (Site not responding. Last check: 2007-11-06)
		a settable latch electrically coupled to the programmable cell unit to latch the single bit from the programmable cell unit into the settable latch;
		a signal-path means for providing a positive feedback between the settable latch and the programmable cell unit, said signal path means being electrically coupled between the programmable cell unit and the output logic gate; and
		a verifying means electrically coupled to the settable latch for verifying the content of the programmable cell unit.
	www.uspto.gov /web/patents/patog/week43/OG/html/1287-4/US06809550-20041026.html (163 words)

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