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Topic: Programmed Data Processor

    Note: these results are not from the primary (high quality) database.

Communication system between local area network stations - Patent 6272210 This is accomplished by a programmed controller operating a switch which disconnects the DAA connected to the central station and connects a current generator to operate the data processing circuit of the station. The modem of claim 1 wherein wherein said data processor is adapted to communicate with at least one of a speaker, a microphone. said current generator being connected to said data processor when said switch means is in said first position, from said office. www.freepatentsonline.com /6272210.html   (2010 words)

Improved Linux* SMP Scaling: User-directed Processor Affinity - Intel® Software Network Depending on the settings programmed in the I/O APIC, interrupts are distributed either to processor(s) specified in the I/O APIC redirection table or the processor that is executing the lowest priority process. The migrated process needs to warm various levels of data caches in the processor that it has just migrated to. In Linux 2.6, a more intelligent scheme is implemented, where the kernel dispatches interrupts to one processor for a short duration before it randomly switches the interrupt delivery to a different processor. intel.com /cd/ids/developer/asmo-na/eng/dc/windows/188935.htm?page=1   (628 words)

Computer History Museum - Timeline Within a decade, research on the optical transistor led to successful work on the first all-optical processor and the first general-purpose all-optical computer. The first optical data storage disk had 60 times the capacity of a 5 1/4-inch floppy disk. Developed by Philips, the disk stored data as indelible marks burned by a laser that could not be overwritten — making it useful primarily for storing large quantities of information that would never need revision. www.computerhistory.org /timeline/timeline.php?timeline_category=cmpnt   (628 words)

Running Programs in Parallel rather than take data to the processors it is possible to take the processors to the data, by implementing a large number of very simple processors in association with columns of bits in memory thus groups of processors can be programmed to work together, manipulating all the bits of stored words. All processors are fed the same instruction in a cycle by a master controller. www.ee.surrey.ac.uk /Personal/R.Webb/l3a15/tsld187.htm   (628 words)

EMC CLARiiON, StorageTek, Backup, Users: Data General Supports both Programmed and Data Channel I/O. Hawk-E. (P/N 9322 E) Basic Hawk Co-Processor card set with 2.0 Mbyte memory and microcoded instructions for Nova 4X and Eclipse S280. This is all it takes to execute your Nova or Eclipse application on a PC with the Hawk Co-Processor. Reboot the PC and run your Nova or Eclipse application on – the Osprey/PC Retire the Nova or Eclipse. www.bltrading.com /nova.htm   (1114 words)

About Excalibur Embedded Processor Solutions The processor features a 16-bit instruction set, user-selectable 16- or 32-bit data paths, and a library of standard soft peripherals configurable for a wide array of applications. This configurable, general-purpose RISC processor can be easily integrated with user logic and programmed into an Altera FPGA. Altera embedded processor solutions can be used in a wide range of applications, from industrial and automotive to access and transmission applications. www.altera.com /products/devices/excalibur/exc-index.html   (431 words)

PC KITS-tutorial page (ISA BUS) The DMA (Direct Memory Access) controller borrows the address bus, the data bus and the control bus from the system and transfers a programmed series of bytes from a fast I/O device to the memory. When the data transfer is completed unasserts the HRQ signal and the processor gets the control of the buses again. When a device has a data block ready to be send to the memory, sends a DMA request asserting a DRQn signal to the DMA controller. www.ctv.es /pckits/tISA.html   (1206 words)

Work Breakdown Structure (WBS) The automatic data process equipment element refers to a machine or group of interconnected machines consisting of input, storage, computing, control, and output devices which use electronic circuitry in the main computing element of automatically perform arithmetic and/or logical operations by means of internally stored or externally controlled programmed instructions. This element includes; for example, a central processor, large-capacity storage data channels, input/output, and that peripheral equipment in operational support of data processing equipment, and devices that are designed to convey data form its original state to a data-processing media. The sensors element refers to those equipments which are used to extend man's natural senses; and equipment which detects and indicates terrain configuration, the presence of military targets, and other natural and manmade objects and activities by means of energy emitted or reflected by such targets or objects. www.nnh.com /ev/wbs.html   (2992 words)

SDI/LCS Seminar Series The computer design features of the CADC were many, including math co-processing, parallel processing, execution pipelining, built-in programmed self-test and redundacy, while yet accomplishing the rigorous requirements of controlling the F14 airplane during combat fighting. The F14 Central Air Data Computer (CADC) was one attempt that accomplished its goal and pushed the technology envelope beyond what was expect in the late ‘60s. Not only did it put the first programmable central processor units onto large-scale silicon, it did it in a hostile military environment. www.pdl.cmu.edu /SDI/2001/092701.html   (2992 words)

23079.980528&ELEMENT_SET=DECL The telecommunication system of claim 1 wherein the interworking unit is configured to process call trigger data and to transmit call trigger data to the signaling processor when the call trigger data is within a subset of call trigger data. For example, if the telecommunication system 102 uses a dual tone multi-frequency signal (DTMF, hereinafter "a tone") as a call trigger, the interworking unit 114 can be programmed through software in the digital signal processor to detect the tone during user communications processing. If the signaling processor 112 determines that the call trigger is valid, the signaling processor may transmit a processor control message to the interworking unit 114 instructing the interworking unit to route the user communications to the third communication device 110 over a selected connection 128. www.wipo.int /cgi-pct/guest/getbykey5?KEY=98/23079.980528&ELEMENT_SET=DECL   (12873 words)

Power supply and power monitor for electric meter - Patent 4591782 In order to provide safe storage for data and/or programmed constants during a power outage, a conventional non-volatile memory 64 is provided into which such data and constants can be written in the event of a power outage and from which the data and constants can be again read upon restoration of normal conditions. This initiates the writing of data from the volatile random access memory in processor 52 to non-volatile memory 64. An electronic processor such as, for example, a microprocessor may be employed to manage the acquisition, storage, processing and display of the usage and demand data. www.freepatentsonline.com /4591782.html   (4400 words)

Eureka Technology - DDR2 SDRAM Controller IP core The SDRAM timing, such as row and column latency, precharge timing, and row access length, are programmed to their default values at system reset. Data between the SDRAM controller and the DDR/DDR2 SDRAM is transferred at both the rising edge and falling edge of the clock input. This allows the SDRAM DDR2 controller to issue precharge, active and read/write commands for the next transfer during the current data access. www.eurekatech.com /products/memory/ep532.htm   (818 words)

DMA reverts to PIO The alternative, slow and inefficient data transfer mode is called PIO, Programmed Input-Output, where the central processor transfers data byte for byte or word for word. This requires many processor commands for each data word and therefore causes a high and unwanted processor load. You can use the procedure described below, but your computer will probably fall back to PIO mode again and again, until you solve the underlying problem, which may be located inside the device, on the motherboard, or in the IDE data cable and its connectors. www.michna.com /kb/WxDMA.htm   (818 words)

Use of other processors during BIOS boot sequence to minimize boot time - US Patent 6336185 A personal computer system as defined in claim 20, wherein said processors are programmed to complete execution of any boot sequence task, after the initiation of the boot sequence task, without reference to data or the execution of any other processor. This is accomplished by creating a parallel boot sequence path for at least one other processor in addition to a boot strap processor, such that this other processor executes certain boot sequence functions that enhance the boot sequence flow, but does not interfere with the boot strap processor (BSP) operation. causing said first peripheral processor to execute a task in said plurality of boot sequence tasks that is different from the task being executed by said boot strap processor and is executed at least partially in parallel with the execution of the at least one task by said boot strap processor. www.patentstorm.us /patents/6336185.html   (3680 words)

United States Patent: 5,559,798 For a given service rate r.sub.i video pre-processor 218 is programmed to minimize costs employing a Viterbi-like process subject to the constraint of source buffer 206 having a size B, and b.sub.i is the amount of compressed video data that actually resides in source buffer during the transmission of interval i video. Such a system is responsive to the rate at which new calls or requests for connections enter and leave the network, the frequency and duration of extended peak rate data bursts, as well as the occurrence of short duration data transmission peaks. In response, the rate value R.sub.0 (associated with the initial segment, S.sub.0, of the particular compressed video data program stored within video source 207) is transmitted from video data transmission rate memory 208 to network renegotiation controller 213. www.eecs.berkeley.edu /~dtse/rcbr2_patent.html   (3770 words)

TcIA_overview.txt The TURBOchannel interface ASIC in Programmed I/O Programmed I/O transactions (PIO) occur in response to a system processor's load/store instructions to the option's slot in the physical address space. TURBOchannel DMA bursts move one word-aligned 32-bit word on the _tc.ad[31..0]_ lines per clock cycle, but for some options the natural data transfer unit (option-word) is 16 or 8 bits. In a TURBOchannel DMA transaction, after a few initial cycles of hand shaking and addressing, the data is moved synchronously at one word per clock cycle. ftp.digital.com /pub/DEC/TriAdd/TcIA_overview.txt   (4761 words)

Vas's M.Phil Chapter 2 Operational Models of Parallel Computers Systolic arrays, however, use that data item to perform a calculation at every processor in the chain before returning a it back to main-memory, see figure 2.4-1. Systolic arrays can be programmed to allow data to flow in several dimensions and several directions around the grid. A large memory at each node holds both programs and data which can be worked on independently of the other nodes. www.gigaflop.demon.co.uk /comp/chapt2.htm   (4761 words)

Advanced network processor - Patent 4525830 Each LDU is programmed by the NDU to recognize and process the data at each subscriber line and instructed by the NDU to down load it's processed data to a selected trunk line director unit (TLDU). The LDU may be provided with a output trunk line over which the data packets may be transmitted to a transmission network or to a packet switching network. Alternatively, data packets for one LDU may be transmitted to the memory of another LDU over a system bus interconnecting all the LDU's so that the other LDU may be used for the actual transmission of the data packets to the transmission network. www.freepatentsonline.com /4525830.html   (4761 words)

* PDP - (Computing): Definition The original aim was to make the first small computers for engineering and departmental use, and the PDP (Programmed Data Processor) range became known as minicomputers to contrast them with giant mainframes... PDP-11 (Programmed Data Processor-11) is one of the most famous computers in computing history, one of a series manufactured by Digital Equipment Corporation () from the early 1960s through the mid-1990s... It looms large in hacker folklore because of its adoption in the mid-1970s by many university computing facilities and research labs, including the,, and... en.mimi.hu /computing/pdp.html   (4761 words)

ipedia.com: PDP-10 Article The PDP-10 was a computer manufactured by Digital Equipment Corporation from the late 1960s on; the name stands for "Programmed Data Processor model 10". The PDP-10 was a computer manufactured by Digital Equipment Corporation (DEC) from the late 1960s on; the name stands for "Programmed Data Processor model 10". Starware search is an excellent resource for quality sites on pdp 10 and much more! www.ipedia.com /pdp_10.html   (4761 words)

papers : paper 2002/3 The connection is based on networking software programmed in the processor device and a gateway server, which together transfer data between the PSTN and other communication networks. Besides the low cost, the proposed system has several benefits, such as uncomplicated structure and operation, standardized data transfer, and an ability to be embedded in an 8-bit processor device. The data communication utilizes the Short Message Service (SMS) and the Extended Machine Interface (EMI) protocol. www.itcon.org /cgi-bin/works/Show?2002_3   (369 words)

index.asp?layout=articlePrint&articleID=CA430897 Recent processor product designs allow unique die identifiers to be programmed at wafer sort based on a combination of lot number, wafer scribe and X-Y probe location. As models are improved that relate wafer sort parametrics with final device performance, this will eventually lead to trusted models for similar relationships between fab metrology data, e-test, wafer sort and final test. AMD Opteron processor yield trend vs. wafer count was steeper than that for prior processor introductions, despite its being a new product on a new 130 nm process. www.reed-electronics.com /SEMICONDUCTOR/index.asp?layout=articlePrint&articleID=CA430897   (369 words)

Embedded Pentium® Processor Family Technical Information Center - Floating-Point Unit Note that the FPU's word-integer data type is identical to the word-integer data type used by the processor's integer unit and the short-integer format is identical to the integer unit's doubleword-integer data type. A pointer to the FPU data register that is currently at the top of the FPU register stack is contained in bits 11 through 13 of the FPU status word. Like the general-purpose registers in the processor's integer unit, the contents of the FPU data registers are unaffected by procedure calls, or in other words, the values are maintained across procedure boundaries. www.engr.udayton.edu /faculty/jloomis/ece314/notes/fpu/fpu.html   (7054 words)

KIM-I Hardware Manual V1.0 The 8 lines of the Peripheral A I/O port therefore contain either input or output data depending on whether the line is programmed to act as an input or an output. Each set of 8 input or output lines (referred to as "PORT") is given an address and the processor simply writes data to that address. At a 1 MHz clock rate, the data on the data bus must be stable 100 ns before the end of Phase Two. www.kim-1.com /hwman.html   (14472 words)

Message formatting, authentication, and error detection in home control systems - US Patent 6690289 An electrical component as recited in claim 32, wherein the shared key value is from a sequence of key values, the processor being further programmed to change from a current to a subsequent key value in the sequence without notifying a receiving component. The message authentication code for a message within a particular group is derived from message data and from a key value that is shared between the components of the group. An electrical component as recited in claim 9, wherein messages composed and sent by the transmitter include message authentication codes that are calculated using a predefined one-way function of data from the messages and of a key value that is shared between components of the particular component group. www.patentstorm.us /patents/6690289.html   (8199 words)

Motorola MC6845 Cathode Ray Tube Controller Internal CRTC registers are programmed by the processor through the data bus, D0--D7, and the control signals -- /W/R, /CS, RS and E. The nineteen registers of the CRTC may be accessed through the data bus. Light Pen (L) The remaining register contents must be determined from some basic data related to the CRT monitor and from the user-desired display format. Vertical registers are programmed in scan line times with respect to the reference as shown in Figure 13. andercheran.aiind.upv.es /~amstrad/docs/mc6845/mc6845.htm   (4325 words)

Embedded Pentium® Processor Family Technical Information Center - Floating-Point Unit Note that the FPU's word-integer data type is identical to the word-integer data type used by the processor's integer unit and the short-integer format is identical to the integer unit's doubleword-integer data type. A pointer to the FPU data register that is currently at the top of the FPU register stack is contained in bits 11 through 13 of the FPU status word. The first Intel Math Coprocessors (the Intel 8087, Intel 287, and Intel 387) were companion processors to the Intel 8086/8088, Intel 286, and Intel386 processors, respectively, and were designed to improve and extend the numeric processing capability of the Intel Architecture. www.engr.udayton.edu /faculty/jloomis/ece314/notes/fpu/fpu.html   (4325 words)

Symmetric multiprocessing - Wikipedia, the free encyclopedia SMP systems allow any processor to work on any task no matter where the data for that task is located in memory; with proper operating system support, SMP systems can easily move tasks between processors to balance the work load efficiently. SMP is only one style of multiprocessor machines; others include NUMA which dedicates different memory banks to different processors. SMP makes this worse, as only one processor can access memory at a time; it is possible for several processors to be starved. en.wikipedia.org /wiki/Symmetric_multiprocessing   (908 words)

Programmed Input/Output - a Whatis.com definition - see also: PIO Programmed Input/Output (PIO) is a way of moving data between device s in a computer in which all data must pass through the processor. The newer Advanced Technology Attachment standard specifies two higher data transfer rates (mode 3 at 11.1 MBps and mode 4 at 16.6 MBps). The Advanced Technology Attachment / Integrated Drive Electronics standard specifies three PIO data transfer rates (mode 0 at 3.3 MBps, mode 1 at 5.2 MBps, and mode 2 at 8.3 MBps). whatis.techtarget.com /definition/0,,sid9_gci214298,00.html   (908 words)

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