| | EDN Access -- 12.8.94 Draw workstation graphics into mainstream PCs |
 | | High-performance RAMDACs derive the proper SCLK and LOAD clock frequencies from their internal pixel-clock rate, not the clock rate on their input pin; that is, for 1600×1280-pixel resolution (170-MHz operation) at 8 bits/pixel (4:1 multiplexing), PCLK1 would be 85 MHz, and LOAD and SCLK would run at 42.5 MHz--or one-fourth the internal pixel-clock rate. |
 | | In addition, the BIOS should copy the contents of the RAMDAC's cursor and color-palette RAM into system memory and shut down the internal RAM to ensure that data are not corrupted by the clock signal, which may be noisy until the PLL locks. |
 | | You can place the RAMDAC over the analog power plane somewhere close to the digital/analog separation; or, place it astride the digital/analog separation so that the pixel inputs are over the digital-supply plane. |
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