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| | VLSI Research Group - Ramy (Site not responding. Last check: ) |
 | | Ramy Aly and Magdy Bayoumi, “Low Power Cache Design Using 7T SRAM Cell”, Accepted and in Press, IEEE Transactions on Circuits and Systems. |
 | | Ramy Aly, Magdy Bayoumi, and Mohamed Elgamel, “Dual Sense Amplified Bit Lines (DSABL) Architecture for Low-Power SRAM Design,” 2005 IEEE International Symposium on Circuits and Systems (ISCAS'2005), May 23-26, 2005, Kobe, Japan. |
 | | Ramy E. Aly, Md Ibrahim Faisal, and Magdy A. Bayoumi, "Novel 7T SRAM Cell for Low Power Cache Design," Proceedings of 18th Annual IEEE International ASIC/SOC Conference, September 2005. |
| www.cacs.louisiana.edu /vlsi/ramy.htm (221 words) |
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