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Topic: Register transfer level

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	Introduction
		Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers.
		Within the logic level the characteristics of a system are described by logical links and their timing properties.
		Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.
	www.asic-world.com /verilog/intro1.html (519 words)

	22C:122/55:132, Lecture 5, Spring 2004
		Register transfer systems are generally described schematically, using notations based on the standard schematic diagram notations developed by electrical engineers.
		Therefore, if a register is located, in the physical realization of the circuit, near some function that requires the inverted outputs, it is common to extract these directly from the register instead of using inverters to compute the function.
		On the other hand, if the inverse is needed at some distance from the register, the cost of the added inverters may be frequently less than the cost of the extra interconnections needed to move both the Q outputs and the Qbar outputs from the register.
	www.cs.uiowa.edu /~jones/arch/notes/05rtl.html (4331 words)

	A computer system is complex in several ways
		Thus the logic level is an instance of the circuit level only in the same sense that the circuit level is an instance of Maxwell's equations-as a limiting case in which certain features are deliberately ignored.
		The register-transfer level is still uncertain because there is substantial agreement neither on the exact language to be used for the level nor on the techniques of analysis and synthesis that go with it.
		One peculiarity of the program level is that there exists no universal representation for it, as there does for the circuit or logic-circuit level (and, it is to be hoped, soon for the register- transfer level).
	europa.nvc.cs.vt.edu /~cegyhazy/cs4014/Chapt1-2A.htm (7312 words)

	VHDL Hardware Description Language (Site not responding. Last check: 2007-10-11)
		High level simulation should be used effectively to detect flaws in the design at an early stage and reduce the need for more detailed simulation.
		RTL synthesis generates structural netlists from a set of register transfer functions.
		The register transfer operations can be described as a finite state machine or a set of register transfer level equations, and include state minimisation, state encoding, logic minimisation, and technology mapping [Figure 3.3 (b)].
	members.tripod.com /o_alshibami/project/ch3.html (1543 words)

	Computer Aids for VLSI Design (Site not responding. Last check: 2007-10-11)
		Register transfer is an environment that is used to describe the design of processors.
		Their level of detail is much greater and fewer assumptions are made about the contents of a component.
		Register transfer has four types of connections between components: bus, control, Boolean, and miscellaneous.
	www.rulabinsky.com /cavd/text/chap02-4.html (1550 words)

	22C:122/55:132, Lecture 1, Spring 2004
		This level, with its focus on switching mechanisms used to interconnect top-level system components, is of primary concern to two groups: First, it is extremely important to the designers of input-output mechanisms.
		This is the focus of the register transfer level, and it is the central issue with which the implementors of an architecture must deal.
		System descriptions at the RT level are frequently done in terms of block diagrams showing data flow between registers, combined with finite state automata descriptions of the control unit that evokes the required data transfers in the appropriate order.
	www.cs.uiowa.edu /~jones/arch/notes/01intro.html (1860 words)

	Power Exploration in High-Level Synthesis
		Working at a higher level of abstraction, the designer enjoys a significant boost in productivity—anywhere from 10-100x—versus RTL or hardware C languages, which over constrain the source by hard coding concurrency, timing and structure directly in the source language.
		Since the lower level code is automatically generated from the system specification, there are fewer bugs introduced into the design—up to 60% less.
		The level of design space exploration possible at a higher abstraction is immensely valuable in determining the optimal design architecture to adopt.
	www.fpgajournal.com /articles_2006/20061219_mentor.htm (1675 words)

	EETimes.com - Built-in self-test migrates to register-transfer level
		EETimes.com - Built-in self-test migrates to register-transfer level
		BIST "was done at the gate level, and there were other issues in terms of automation," said Healy.
		The first is ETChecker, which analyzes the RTL design for rule violations and extracts the information that LogicVision needs to add embedded test.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=163702305 (548 words)

	SOCcentral: Why Haven't EDA Vendors Given Us DFT at the Register Transfer Level? (SOCcentral 13071)
		Today, it is mandatory to consider testability issues very early in the design process and it is not acceptable for an RTL designer to deliver synthesizable code in Verilog or VHDL with testability problems (that is, with test vectors of poor quality).
		Implementing at the register transfer level also will accelerate delivery of soft IP cores, which means a better predictability of the overall design cycle time.
		For instance, for RTL ISCAN, implementation should be first at the IP core level before complete adoption at the level of the SoC.
	www.soccentral.com /results.asp?catid=488&entryid=13071 (896 words)

	OhioLINK ETD: MANSOURI, NAZANIN
		Contributions of this research include formalization and formulation in higher-order logic in a theorem proving environment mathematical models for the synthesized register transfer level designs and their behavioral specifications and a set of sufficient correctness conditions for these designs.
		CCG generates (1) formal specifications of the behavior and the RTL design including the data path and the controller, (2) the correctness lemmas establishing equivalence between the synthesized RTL design and its behavioral specification, and (3) their proof scripts that can be submitted to a higher-order logic proof checker.
		This approach is based on the identification, by the synthesis tool during the synthesis process, of the binding between critical specification variables and criticalregisters in the RTL design and between the critical states in the behavior and the corresponding states in the RTL design.
	www.ohiolink.edu /etd/view.cgi?ucin982064542 (495 words)

	Projects
		RTL level power estimation: At the Register Transfer Level, the estimation of the maximum current in a power gated circuit must determine the maximum of all possible power-up and normal switching current.
		We developed a register transfer level leakage estimation considering a rich cell library at ISPD'01 [C20], ASP-DAC'02 [C25], and an IEE journal paper [J20], We proposed a cluster-based ATPG algorithm to estimate the maximum power-up current for combinational circuits.
		Experimental results showed that the maximum power-up current for sequential circuits can be up to 73% larger than the maximum normal switching current.
	eda.ee.ucla.edu /projects/uArch_RTL.html (768 words)

	System-Level Sideshow
		On the true "system" level, ESL tools allow us to model our systems in a virtual prototype using abstract, high-level languages that don't distinguish between what functionality is implemented in hardware or software.
		Once we have part of the system design earmarked as hardware, we move to the lowest level tools that are still frequently "ESL" branded – high-level hardware synthesis.
		Running parallel to all these levels of ESL abstraction are graphical design and analysis tools that allow viewing, block level description, and control of the whole tool flow.
	www.fpgajournal.com /articles_2006/20060711_sideshow.htm (1854 words)

	EDA DesignLine \|
		An emerging trend is a transaction level modeling (TLM)-to-register transfer level (RTL) design flow, though a set of requirements needs to be addressed to ensure a successful transition to this new flow.
		The advancement of the chip manufacturing technology with process nodes moving from 130nm to 90nm to 65nm and even smaller geometries have an impact on chips on the drawing boards today, and render as ineffective an RTL-only flow as ineffective.
		Since the TLM result compares to RTL code and RTL code needs to be included in simulation, models need to have cycle-accurate interfaces.
	www.edadesignline.com /GLOBAL/electronics/designline/shared/article/showArticle.jhtml?articleId=196900909&pgno=1 (1100 words)

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	IEEE Approves Computer Standards for Verilog RTL and STIL
		One new standard, IEEE 1364.1(TM), "Standard for Verilog Register Transfer Level Synthesis," develops a standard syntax and semantics for Verilog RTL synthesis.
		It defines the subset of IEEE 1364 (TM) (Verilog HDL) suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain.
		All other names or product names are the trademarks, service marks or registered trademarks of their respective holders.
	standards.ieee.org /announcements/verilogrtlstil.html (533 words)

	rtlib: register-transfer level
		The current implementation is limited to buses at most 63-bit wide, due to its use of a very compact storage scheme.
		The processor is kept as simple as possible, to teach the basics of the von-Neumann machine paradigm.
		The 8-bit accumulator machine is built from just four registers (accumulator, program counter, instruction register, and address register), the ALU, one incrementer, two multiplexers, and the main memory:
	tech-www.informatik.uni-hamburg.de /applets/hades/webdemos/rtlib.html (344 words)

	CITIDEL
		THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level.
		Certain assumptions are made regarding the RT level of design, and a model for data part designs is postulated.
		We analyze different methods of generating addressing code for scalar variables and quantify the improvements due to optimizations such as offset assignment, modify register optimization and address register assignment.
	www.citidel.org /?op=browse&scheme=ccs1998&node=38 (1043 words)

	Forschungszentrum Informatik (FZI) -
		The reduction of lower level details increases not only the complexity which can be handled by the human designer and the synthesis system.
		It shifts also the type of knowledge, which is required from the designer, from electronic/technical knowledge to a more system oriented views.
		Up to now there are numerous commercial tools at logic level and at register-transfer level available, but there are just a few commercial tools at higher levels.
	www.fzi.de /sim/caddy.html (408 words)

	Srivaths Ravi, Publications (Site not responding. Last check: 2007-10-11)
		My research on high-level testing has dealt with the problem of generating test patterns from a register transfer level (RTL) description of a circuit in order to detect stuck-at faults in the circuit at the logic level.
		The methodology has also been shown to be applicable to other domains such as built-in self-test at the RTL and system-on-a-chip test generation.
		My recent research has also led to the development of a scalable processor self-test methodology, wherein, we demonstrated the first ever application of the paradigm to an industrial processor.
	www.princeton.edu /~sravi/test.htm (482 words)

	Search Results: IEEE Standards Status Report
		It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain.
		This standard shall define the subset of IEEE 1076 (VHDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain.
		The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with thesemantics of that subset for the synthesis domain.
	standards.ieee.org /cgi-bin/status?1076.6-1999 (861 words)

	Register transfer level - InterDok - MInd: The Meetings Index (Site not responding. Last check: 2007-10-11)
		We present design for low power techniques based on glitch reduction for register transfer level circuits.
		An Introduction to Register Transfer Level Simulation of Digital
		Name of event:, Register Transfer Level and High Level Testing, 2006 International Workshop.
	instanceweb.com /isnw/register-transfer-level.html (173 words)

	CITIDEL
		A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented.
		A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures.
		This paper presents a non-scan design-for-testability technique applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures.
	www.citidel.org /?op=browse&scheme=ccs1998&node=42 (768 words)

	Synopsys delivers Verilog RTL subset - register-transfer-level documentation - Company Business and Marketing ...
		Along with the Verilog RTL subset delivery, Synopsys also said VHDL synthesizable subset documentation is nearing completion and will be released shortly.
		The standardization effort began as part of the implementation phase of the EDA Industry Standards Roadmap, for which the RTL subset was identified as one of the high-priority, technology transfer projects necessary for implementation.
		"Standard synthesizable RTL is the first step toward standards for design reuse," said Larry Woodson, senior VP of corporate marketing at Synopsys.
	www.findarticles.com /p/articles/mi_m0EKF/is_n2136_v42/ai_18738430 (716 words)

	The Altera System FPGA Partners Program (Site not responding. Last check: 2007-10-11)
		System-level design methodologies utilize higher level languages for system development and architecture exploration, and can lead to increased productivity, faster time-to-market, higher quality of results, and reduced risk.
		In the hardware flow, the system design tool optimizes algorithms and generates register transfer level (RTL) code or a gate-level netlist targeting the FPGA.
		The RTL code or gate-level netlist can then be imported to the Quartus
	www.altera.com /products/software/partners/system_level/sys-index.html (304 words)

	Browse :: The Register Books - IT and Computer Book specialists
		The text's focus on register-transfer-level design and present-day applications not only leads to a better appreciation of computers and of today's ubiquitous digital devices, but also provides for a better understanding of careers involving digital design and embedded system design.
		* An emphasis on register-transfer-level (RTL) design, the level at which most digital design is practiced today, giving readers a modern perspective of the field's applicability.
		Yet, coverage stays bottom-up and concrete, starting from basic transistors and gates, and moving step-by-step up to more complex components.
	books.theregister.co.uk /catalog/browse.asp?ref=818750&advert=regrelat (301 words)

	[No title] (Site not responding. Last check: 2007-10-11)
		(c) analyzing the first register transfer level code to identify a global multiplex structure connected to a total number of signal lines that exceeds a user defined threshold of a number of signal lines in the user defined optimum multiplex structure;
		(e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures; and
		(f) replacing a global control block with a plurality of local control blocks in the second register transfer level code.
	www.uspto.gov /web/patents/patog/week31/OG/html/1309-1/US07086015-20060801.html (189 words)

	LinuxElectrons - Concept Engineering Introduces RTLvision PRO
		RTLvision PRO helps engineers reach faster RTL code closure by enabling quick visualization of critical design fragments and easy understanding of design behavior and design miss behavior.
		This easy-to-use, high-performance tool helps reduce the complexity of the debug process via its interactive logic cone navigation feature, which shows just the critical portion of the RTL design in the logic cone window while concurrently providing links to the original source code.
		As a result, engineers can easily work on the important critical fragments of their RTL project without being disturbed by code and graphics not relevant for the job at hand.
	www.linuxelectrons.com /article.php?story=20060707122845424 (456 words)

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	AutoESL - The Easiest Path from ESL to Silicon
		traditional register transfer level (RTL) methods, and it is commonly acknowledged
		that the ultimate solution is to move to the next level of abstraction beyond RTL.
		Electronic system level (ESL) design automation has been identified as the next
	www.autoesl.com (191 words)

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