
	Where results make sense

Topic: Routing (EDA)

	EDAC
		EDA software tools or tool suites which may display simulator output for analysis (as in waveform analyzers) or which may analyze the reliability, electromagnetic interference, metal migration, signal integrity, or thermal characteristics of a design.
		An EDA or supply chain application which allows users to locate components and suppliers, view parametric information about the component, conduct procurement transactions, and in some cases to even obtain design views of the selected components that can drive their particular EDA design tools of choice.
		EDA software tools that provide an environment where issues such as timing, area, power dissipation, and routeability can be analyzed before a detailed physical layout of a design is completed.
	www.edac.org /industry_glossary.jsp (6213 words)

	ProteusShape Based Autorouting with Connect EDA Electra (Site not responding. Last check: 2007-10-17)
		This method is best used where a suitable routing strategy has been established and saved in a DO file, and there is a need to route the board repeatedly as the design evolves.
		The start_pass parameter should only be used on the second or subsequent routing commands and sets the initial costing of the first routing pass of that route set.
		If ELECTRA places routes that cause a power plane to be broken into two or more unconnected areas of copper, it is unable to detect that this has occurred and the board will show one or more missing connections when imported back into ARES, even though ELECTRA has claimed 100% completion.
	www.labcenter.co.uk /support/electrasupp.htm (1396 words)

	CTAS - En Route Descent Advisor (EDA) (Site not responding. Last check: 2007-10-17)
		EDA works in conjunction with the CTAS Traffic Management Advisor (TMA), which generates the precise schedules and sequences that EDA targets for optimal throughput into the TRACON.
		EDA is capable of generating explicit ``meet-time'' maneuver advisories based on combinations of speed, altitude, and heading degrees of freedom.
		Finally, with assistance from EDA under high-workload metering conditions, controllers will be able to focus additional attention on non-metering tasks, such as responding to changing weather and airspace conditions, and accommodating user route preferences.
	www.ctas.arc.nasa.gov /project_description/eda.html (515 words)

	EDACafe : Vision Printer Friendly Vresion
		Unfortunately, EDA design and validation tools are fragmented and each relies on its own proprietary database, which supports only the functionality of that tool.
		Coexisting with other EDA tools, the new system could be most effectively used at the front end to resolve the design and engineering issues early in the design stage.
		The system's EDA applications would run on the client machines, thus allowing the intellectual properties of designs to remain behind the customer's firewall; reducing delivery costs; and preventing the system performance from being degraded by increased simultaneous user access.
	www.edavision.com /printer_friendly.php?article=200206/tool2.html (3141 words)

	EDA Industry Primer (Site not responding. Last check: 2007-10-17)
		EDA technologies of one form or another are now in use by most working engineers in all parts of the world.
		EDA tools are available from literally dozens of individual product vendors, ranging from large Fortune 500 companies such as Cadence and Intergraph to small, focused companies offering "point solution" products.
		The biggest news in EDA tools today is a shift away from high cost, workstation-based tools to more flexible, lower-cost tools that are available on personal computer platforms.
	www.acc-eda.com /about/eda.html (437 words)

	Bartels AutoEngineer User Manual - Autorouter (Site not responding. Last check: 2007-10-17)
		Each routing grid change is stored with the layout and also sets the standard trace width and minimum clearance distance values to the default settings for that grid (see table 4-1 for the grid-specific default values).
		Routing with via offset means that vias can be shifted by half the routing grid at their placement.
		Routing with via offset may well allow to use channels which would otherwise be occupied by in-line placed via on adjacent grid channels.
	bartels.de /baedoc/bm4_05_en.htm (5903 words)

	X Architecture: The Year of Production Silicon
		The X Architecture is said to reduce the total wiring on a chip by more than 20 percent and reduce vias by more than 30 percent, thus improving the performance, power, and cost of the chip.
		In the place and route flow, placement wire length minimization and congestion estimation enhancement need to assign nets to three sets in order to minimize wire length, to improve timing performance, and to reduce congestion/wire length.
		On the other hand, the X architecture does tend to improve routing characteristics -- especially decreasing the number of vias relative to Manhattan routing -- which will tend to improve yield, especially for chip with a large number of routing layers.
	www.edat.com /NEA24.htm (923 words)

	[No title] (Site not responding. Last check: 2007-10-17)
		In short, the EDA industry has come of age, but the future of the industry is far from certain.
		The recent work on statistical static timing is an example of the response of the EDA community to this important area.
		Sitting around a potbellied stove, in their rocking chairs, practitioners of that era (and this) will offer insight into why some great ideas were immediately put into practice while others stayed on the drawing board or in the ivory tower.
	www.dac.com /tempprint/webfile/41DACSessions.txt (6450 words)

	EETimes.com - Nanometer IC routing requires new approaches
		Getting early access to useful wire information requires access to smart routing technology that has the capacity and flexibility to correctly route multiple millions of nets flat, and can be leveraged during silicon virtual prototyping, logical/physical optimization and clock tree synthesis.
		Using detail routing information as the basis for early design trade-offs during silicon virtual prototyping is key to accurate timing and SI prediction and prevents surprises from occurring late in the design cycle when they are much more difficult, time consuming, and expensive to resolve.
		Routing optimization features should include explicit per-net length controls to avoid detoured or scenic routes and create as many short point-to-point connections as possible.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=17408869 (2713 words)

	Routing in Pantheon PCB / Hybrid / RF Design
		Routing in PANTHEON is accomplished with a single-connection, from-to automatic router, as well as an interactive router with a complete set of interactive routing modes, features and functions.
		While routing, use the push-and-shove feature to move wires and vias, creating room for the currently routed wire.
		Splash components and vias into a densely routed area and watch PANTHEON clear the area for a new route, or clean up the area if a via or wire is removed.
	www.intercept.com /html_files/products/pantheon/routing.htm (358 words)

	Real-time, impedance-controlled routing
		Impedance-controlled routing is an excellent technique for minimizing potential signal integrity issues on a board.
		The PCB rules-driven design environment leaves you free to focus on laying out and routing the board, while your critical design requirements are automatically monitored and managed by the system.
		During interactive routing the software will automatically calculate the width required on the current layer in accordance with the defined layer stackup and materials, maintaining the specified impedance requirement.
	www.altium.com /Evaluate/DEMOcenter/MovingfromProtel99SE/Impedancecontrolrouting (206 words)

	Proteus EDA/CAD - PCB Design Software (Site not responding. Last check: 2007-10-17)
		Topological route editing allows you to re-route or delete any section of a track, irrespective of how it was originally placed.
		The range of routing grids available enables you to trade off routing density against execution speed with densities of 1, 2 or 3 traces between IC pads.
		During manual routing, ARES checks each track as you place it and warns you if any design rules (physical/electrical) are broken.
	www.labcenter.co.uk /products/pcblayout.htm (1224 words)

	New IC Routing Start-up Company - Pulsic - is Officially Announced
		Pulsic's mission is to provide the ultimate routing product in terms of performance, completion and quality of result, to address the increasingly demanding challenges of analog, custom, mixed-signal and system-on-chip (SoC) design.
		The founding members of Pulsic and its senior consultants have over 70 years of accumulated EDA experience, specifically in the field of routing.
		Lyric is based on the company's new and ground-breaking routing technology, called T-route™, which has evolved from shape-based techniques, and is where Pulsic's expertise is firmly entrenched.
	www10.edatoolscafe.com /nbc/articles/view_article.php?section=CorpNews&articleid=14932 (907 words)

	Bartels Autorouter® (Site not responding. Last check: 2007-10-17)
		The off-grid feature is a combination of grid-based and gridless routing technologies and does off-grid routing of traces even in a cell-based environment, making it the ideal combination between cell-based and shape-based technologies.
		With the introduction of the sub-grid mode, the on-grid limit for routed traces was relaxed to half-grid (one-half) shifted traces, thus permitting proper handling of fine pitch SMT.
		The strategic trace routing is done via the matrix, thus both the advanced Lee algorithm which guarantees to find the least cost optimum way for a single trace, and the Bartels RipUp and CleanUp algorithms which detect optimum traces for rip-up and cleanup, can be used together with a non-rectangular shape-based database.
	bartels.de /bae/baear_en.htm (1170 words)

	routing - OneLook Dictionary Search
		ROUTING, routing : Glossary of Global Trade Terms [home, info]
		ROUTING : Space and Electronic Warfare Lexicon [home, info]
		Phrases that include routing: adaptive routing, classless inter domain routing, source routing, hot potato routing, routing protocol, more...
	www.onelook.com /?w=routing (245 words)

	CSD Magazine - September, 1998 - Standards & Protocols
		Remember that by “dense mode,” I am referring to a type of multicast routing that is used when the information source and recipients are relatively close (in terms of routing hops) to one another.
		As each router receives a packet requiring a new multicast route, it traverses its link state database to identify the direction(s) in which a multicast packet must be routed to reach all interested destinations.
		If we take as an example the routing topology shown in Figure 2, there are a set of routes that are used for multicast forwarding and a separate set of routes that do not warrant transmission of the multicast routes.
	www.commsdesign.com /main/9809/9809sp.htm (1654 words)

	Product Listing: IC Physical Design Tools
		Blast Chip is the industry's only synthesis, place and route solution that does not rely on inaccurate wire load models or initial placement data to determine cell size.
		The ultra high-speed global routing engine not only guides the automatic routing, enabling large designs to be routed more rapidly and completely, but also provides visual and quantitative analysis of the congestion in the design - highlighting problem areas that can be fixed within the application by easy incremental adjustments to the floorplan.
		The router quickly provides optimal linear channel trunk routing which is then intelligently understood by the application, so other tools within the Lyric Framework will obey the special rules that apply to them.
	ecat.edacafe.com /product_list.php?category_id=1000048 (3173 words)

	Electra
		Our staff of highly skilled EDA developers, with extensive autorouting software development background, is committed to develop and market high quality Adaptive Shape-Based Automation Software.
		Adaptive routing algorithm is the only proven approach to reach high completion rate.
		Routing results are saved into standard route file format (RTE) or session file (SES).
	www.csieda.com /electra.htm (207 words)

	EETimes.com - EDA pioneer takes startup to new routing ground
		Cooper said that TeraRoute is working with four large chip-design companies, and is developing a platform that can handle "everything from standard-cell routing to chip assembly and memory routing." He said TeraRoute expects production-ready code by the first or second quarter of 2006.
		The chief thing that's unique about the TeraRoute technology, he said, is the way in which it handles the internal data flow of the routing program.
		Given that large EDA vendors all have their own IC routers, is there a need for a third-party tool?
	eet.com /issue/mn/showArticle.jhtml?articleID=169400764 (715 words)

	Software Feature - Routing All forms of trace routing are accomplished with power any angle routing features Trace ...
		Routing is CDS’s object based routing system that “hugs” objects with exact clearance, and speeds up the trace routing process.
		The routing system features drilled and build-up via technologies, with support for through hole, blind, buried, and stairstepped via constructions.
		Ability to route traces by using polygon boundaries.
	www.cad-design.com /software/routing_technology.html (271 words)

	EDA Tech Forum - September 2005
		EDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia.
		EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends.
		EDA Tech Forum publishes the first of the two ‘best of ’ papers from the 2005 Design Automation Conference.
	www.edatechforum.com /journal/sept2005 (347 words)

	EETimes.com - Routing technology came from within Cadence, execs say
		According to executives from both companies, Brashears met with IBM in 2002 to demonstrate a new core routing architecture and implementation of algorithms.
		Stok said he and other IBM representatives immediately latched on to the routing technology, as well as the componentization and modulation of the architecture.
		According to Brashears, the routing technology created by Cadence generates opportunities for in-depth collaboration because its architectural core components can be exposed to enable development of solutions to design-for-manufacturability related convergence issues.
	www.eetimes.com /news/design/showArticle.jhtml?articleID=192700243 (878 words)

	VAMP Inc.-- Macintosh Product Line
		Up to 16 layers can be routed at breakneck speeds as all of these applications are available in native for the Power Mac user.
		This router incorporates multiple routing technologies including some Push and Shove capabilities and is intelligent enough to handle complex layouts with typical completion percentages from 90 to 100 percent depending on user set parameters.
		This router is capable of routing a board in two layers that would require 3 or 4 layers on other Mac OS autorouting platforms.
	www.mccad.com /MacCAD.html (3794 words)

	Wolf's Witterings : A Comparison of Service Oriented Architecture (SOA) and Event Driven Architecture (EDA)
		About the only similarities that I could argue that SOA has with EDA are that a) they are both badly named (although I will definitely agree the SOA is a much less informative name than EDA) and b) they are not architectures but rather design paradigms.
		EDA is all about Message routing, part of the system that SOA says nothing what so ever about.
		There are basically two methods of defining message routing; it can be predetermined – flow based – such as you might see in a traditional, client server type application, a “new age” BizTalk Orchestration or even a “prehistoric” Mainframe JCL job.
	blogs.msdn.com /mikegil/archive/2005/01/21/357953.aspx (1229 words)

	MINT Group Projects: STEED - EDA Benchmark and Testdata
		For these benchmarks the quantitative measure of routing performance is the maximum routing channel width for 100% routing.
		Low-Level synthesis is the term used to address the issues associated with technology mapping and in some cases the physical placement and routing of a design.
		From the perspective of the benchmark data, the logic synthesis process involves processing a generic functional netlist and mapping functional components to those in the target technologies library and then placing and routing the mapped netlist conforming to various constraints associated with the target technology.
	mint.cs.man.ac.uk /Projects/STEED/benchmarks.html (1733 words)

	EDN - Quadruple-duty EDA tool promises first-pass chips - 5/13/2005 - EDN - CA601305 (Site not responding. Last check: 2007-10-17)
		EDA startup Silicon Design Systems (SDS) this week made available its K-Route tool, which the company claims performs extraction, timing analysis, and signal-integrity analysis during detailed routing to help designers complete an optimized ASIC or SOC design in hopefully one pass.
		Those large cycles between routing, timing, extraction and signal-integrity analysis consume time and are error-prone, as one timing fix can turn into three signal-integrity problems in the following routing-through-analysis cycle, said Dubi Margalit, SDS' vice president of product marketing.
		To shrink overall routing time, K-Route incorporates built-in RC (resistance-capacitance) extraction, timing, and signal-integrity engines on top of the detailed routing engine.
	www.silicon-value.com /newsroom/05/Quadruple_duty_EDA_tool.htm (668 words)

	EDA Software of EWB
		Ultiboard is a powerful, yet easy-to-use PCB layout and routing program that delivers the features and flexibility you need to effectively build reliable boards.
		Ultiboard offers a unique combination of advanced functionality and exceptional easy of use: a combination that has made Electronics Workbench the leading provider of EDA tools.
		It is one of the most advanced autorouters in the world and the industry's only tool with both grid and gridless routing.
	www.ultiboard.com /p.html (205 words)

	EDACafe: ASICs .. the Book
		Routing is a complicated problem best divided into two steps: global and detailed routing.
		Two main approaches to global routing are: one net at a time, or all nets at once.
		Routing is divided into global and detailed routing.
	www.edatoolscafe.com /books/ASIC/Book/CH17/CH17.5.php (244 words)

Try your search on: Qwika (all wikis)