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Topic: SSE2

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	SSE2 - Team Hack-a-Day Wiki (Site not responding. Last check: 2007-10-13)
		SSE2 is one of the IA-32 SIMD instruction sets, first introduced by Intel with the initial version of the Pentium 4 in 2001.
		SSE2 has itself been extended by SSE3, also known as "Prescott New Instructions", introduced by Intel to the Pentium 4 in early 2004.
		SSE2 adds support for 64-bit double-precision floating point and for 64, 32, 16 and 8-bit integer operations on the eight 128-bit XMM registers first introduced with SSE.
	www.teamhackaday.com /wiki/index.php?title=SSE2 (286 words)

	Intel SSE2
		SSE2 extends MMX by using 128-bit registers instead of 64-bit ones, effectively doubling the level of parallelism.
		Replacing 64-bit shifts with 128-bit ones is trivial, but SSE2 expects memory references to be 16-byte aligned: while the MOVUPD instruction lets you load unaligned memory blocks at the expense of poor performance (so it should be not used unless strictly necessary), every instruction that uses a memory source operand, e.g.
		An interesting opportunity for optimization comes from the separate MMX and SSE2 register files: it may be possible to unroll a loop by two and code an iteration using MMX and the other one using SSE2, therefore having 16 available registers instead of only 8.
	www.tommesani.com /SSE2MMX.html (1862 words)

	Intel SSE2 Preview (via CobWeb/3.1 planetlab2.netlab.uky.edu) (Site not responding. Last check: 2007-10-13)
		SSE2 is designed to fix this problem: it supports both 32-bit and 64-bit floating point values, but keeping the data block size fixed to 128-bits means that SSE2 instructions can only process two 64-bit data values in parallel.
		What’s more, peeking at the Pentium 4 microarchitecture reveals that the performance gain achieved by using SSE2 could actually be much greater than 2x, as the scalar FP unit suffers latencies that are much longer than on the P6 core, while the SSE2 unit is streamlined to offer blazing speed.
		The conclusion is that developers may be forced to use SSE2 instructions to effectively harness the FP power of the Pentium 4, and that the speed of current FP-intensive applications should be disappointing, considered the 2.0+ Ghz core frequency.
	www.tommesani.com.cob-web.org:8888 /SSE2Intro.html (555 words)

	SSE2 - Wikipedia, the free encyclopedia
		AMD's implementation of SSE2 on the AMD64 platform includes an additional 8 registers, doubling the total number to 16 (XMM0 through XMM15).
		When legacy FPU software algorithms are ported to SSE2, certain combinations of math operations or input datasets can result in measurable numerical deviation.
		Therefore, it is possible to convert all existing MMX code to SSE2 equivalent.
	en.wikipedia.org /wiki/SSE2 (784 words)

	SSE2 for Dummies (who know C/C++) (Site not responding. Last check: 2007-10-13)
		SSE2 is an extension of assembly language which allows programs to execute one operation on multipule data at a time.
		Because SSE2 is assembly however, it only works on processors that support it and fail misserably on anything else.
		A full list of sse2 operations and a description of each can be found at HAYES Technologies.
	dustbunny.physics.indiana.edu /~dwiel/SSE2.html (751 words)

	GameDev.net - SSE2 for Dummies (who know C/C++)
		SSE2 is an extension of assembly language which allows programs to execute one operation on multiple pieces of data at a time.
		A common mistake made by people new to SSE2 is to convert a lot of their old and future code into SSE2.
		If you have an application that is doing a small number of operations on a large data set, you can expect to be less efficient than if you are doing a lot of operations on a small amount of data.
	www.gamedev.net /reference/articles/article1987.asp (1188 words)

	SSE2 - or the death of your machine. « kfsone’s pittance
		SSE2 are SIMD register like the MMX part of your processor.
		I’m not doing anything 64-bit specific, but the SSE2 instructions don’t give you as much of a boost on a 32-bit CPU as they do on a 64-bit CPU, and I couldn’t be arsed to respond to all the 32-bit folks saying “omg its exactly the same” for this experiment.
		However: SSE and SSE2 instances of the client may be part of the 1.24 performance enhancements.
	kfsone.wordpress.com /2006/05/31/sse2-or-the-death-of-your-machine (1965 words)

	[No title]
		SSE2 code is also generated by the compiler for some specialized operations.
		By emitting SSE2 code to perform float-to-int conversions, there is no need to alter the x87 rounding mode control for conversions.
		SSE2 code is also employed for shifting of 64-bit integer quantities.
	www3.intel.com /cd/ids/developer/asmo-na/eng/dc/games/43867.htm?page=8 (683 words)

	SSE2 performance optimization.
		For example SSE2 command set is capable of adding 4 32-bit or 8 16-bit machine words at once.
		SSE2 provides vector instructions for all bitwise operations like AND, OR, XOR or shifts.
		In SSE2 mode all bitwise block pointers must be 16-byte aligned to avoid crashes.
	bmagic.sourceforge.net /bmsse2opt.html (1187 words)

	Processors - Define SSE2 and SSE3 (via CobWeb/3.1 planetlab2.netlab.uky.edu) (Site not responding. Last check: 2007-10-13)
		The SIMD integer instructions introduced with MMX technology have been extended from 64 to 128 bits, doubling the effective execution rate of SIMD integer type operations.
		Double-precision floating point SIMD instructions allow for two floating-point operations to be simultaneously executed in the SIMD format, providing support for double-precision operations that help accelerate content creation, financial, engineering, and scientific applications.
		SSE2 instructions allow software developers to have maximum flexibility to implement algorithms and provide performance enhancements when running software such as MPEG-2, MP3, 3D graphics, etc.
	www.intel.com.cob-web.org:8888 /support/processors/sb/cs-001650.htm (206 words)

	SSE2 makes Opterons slower than Athlon XPs - DriverHeaven.net
		He claimed that even degrading the Athlon XP to 1.6GHz it will still deliver 8933, meaning, he adds that the Opteron's performance is 30% lower on a clock per clock basis.
		He concludes that using SSE2 on the Opteron actually drags down its multimedia integer performance.
		When he reset the SSE2 checkbox for TMPGEnc, he said, "questioning his own hypothesis", its performance far exceeded the Pentium 4-2.8GHz.
	www.driverheaven.net /showthread.php?t=15121 (423 words)

	Sse2 - Getting started with SSE/SSE2 for the Intel Pentium 4 Processor
		SSE2 extends MMX by using 128-bit registers instead of 64-bit ones,
		The bn_mul_add_words routine of openssl-0.9.7c was modified to use the SSE2 pmuludq instruction, which performs a 32-bit x 32-bit -> 64-bit multiply.
		SSE2 code seems to be faster than mmx, > xmm (good point).
	xn--0xqw63g.com /?q=sse2 (331 words)

	Why use Crunch3r SSE2 on SSE3 Processors?
		Found the difference between the SSE, SSE2 and SSE3 crunch times was not measurable.
		With the SSE2 version usually being the one that was a few seconds faster.
		I just do a test for SSE2 and SSE3 on the same short WU, the result shows that there is only a very little different between this 2 program.
	setiathome.ssl.berkeley.edu /forum_thread.php?id=29779 (1115 words)

	brand new ffdshow SSE2 preview - 08/01 - Home Theater PC News
		The preview version is highly-optimized for Lanscoz resize (up to tap of 4) and denoise 3D (with a new "Fast" mode).
		SSE2 is a vector extension present on both P4 and Athlon 64 processors.
		The optimizations that he has done of late are based on the new capabilities that those instructions provide.
	www.htpcnews.com /forums/index.php?showtopic=5685 (884 words)

	SSE2 assisted RSA (Site not responding. Last check: 2007-10-13)
		However for the purposes of evaluating this patch for use in 32-bit libraries compiled for all SSE2 platforms it makes sense to compare the 32-bit number on Opteron.
		It can be seen that on all SSE2 platforms this new code yields improved results over the 32-bit integer code.
		This is because there is never any need for more than 64-bits per register, and better parallelism may be achieved on Pentium-M, Opteron, and Efficēon which implement SSE2 using a pair of 64-bit MMX units (whereas P4 uses a single 128-bit unit).
	www.arctic.org /~dean/crypto/rsa.html (352 words)

	SSE2 in Barton!!???? - Overclockers Forums
		People are saying that Barton has SSE2, if so, that is going to be one heck of a CPU.
		As for what it is, SSE2 is a SIMD (single instruction multiple data) addition to the x86 instruction set that accelerates certain floating point and interger computations.
		Don't think it will have sse2, but i just read an artictle over at the inqirer that says that barton will have soi, hence why they have pushed it back some more.
	www.ocforums.com /showthread.php?t=123035 (625 words)

	Pentium 4 (SSE2) build of mpp tools? - Hydrogenaudio Forums
		I don't know whether mppenc already uses this feature, but if not it would be nice to see the performance in mpc aswell.
		And no, MPC is not SSE2 optimized in any way.
		Like Dibrom says, the SV8 source has been available for a while now, and it is a simple task to disassemble mppenc.exe and see it uses no sse2 instructions to do its processing.
	www.hydrogenaudio.org /forums/index.php?showtopic=4758 (527 words)

	XMM SSE2 floating point instructions (Site not responding. Last check: 2007-10-13)
		These are SSE2 (streaming SIMD extensions) floating point instructions which use the 128-bit XMM registers and which can handle double-precision (64-bit) floating point values.
		Support for SSE2 was introduced in the Pentium 4 and Xeon processors.
		Generally the instructions are very similar to the SSE floating point instructions except for the data size that they work with.
	www.jorgon.freeserve.co.uk /TestbugHelp/XMMfpins2.htm (1037 words)

	The PC Guide Discussion Forums - Intel MMX, SSE and SSE2
		Streaming SIMD Extensions 2 or SSE2 encompasses 144 new instructions, which include instructions for memory and Cacheability management.
		SSE and SSE2, however, are instruction sets that improve floating point operations (again, I'm no expert).
		AMD may have plans to implement SSE2 on their next wave of procs, we'll have to see.
	www.pcguide.com /vb/printthread.php?t=14520 (969 words)

	Five Tips to Turbocharging Windows Codecs with AMD64
		That's not because the actual migration of the codec from 32 bits to 64 bits is hard, but because multimedia encoders/decoders play such a vital role in the performance of the final application, and also because many codecs include assembly code.
		Here are five tips that I can suggest to help the porting process: focusing on SSE and SSE2, using portable scalable data types, using intrinsics, leveraging 64-bit general purpose registers, aligning memory accesses and providing prefetch hints.
		For Win32 applications, those instruction extensions include SSE, SSE2, MMX and 3DNow!, and all four extensions can be used under both 32-bit and 64-bit Windows running on the AMD64 architecture.
	www.devx.com /amd/Article/20923 (1048 words)

	How to test for SSE2 capable CPU and Intel Chipset - MSFN Forums
		I would like to add ffdshow to my unattended installation but there are SSE2 special versions available so in case a SSE2 capable CPU is present, an optimized version should be installed of course.
		What this does is that the output of chkcpu gets redirected to the first findstr, which finds the line with "SSE2", then that output gets redirected to the 2nd findstr which tests for "No" in the output of the previous command.
		This is because the script checks for "SSE2" and "No" but strangely enough, CHKCPU will not mention SSE2 at all if the processor does not even support SSE.
	www.msfn.org /board/index.php?showtopic=35423 (2407 words)

	IGN Boards - SSE2
		The version we had was seriously bugged with a lot of glitches (battles didn't wotk, campaign map was full of graphics errors).
		However, from what we know it seems that all these bugs were caused by the early stage of the beta, not by system requirements of the game.
		No matter what will be the final of this whole issue, keeping thousands of fans in uncertainty and shortage of information about requirements clearly shows that decision makers at SEGA are far away from being proffesionals.
	boards.ign.com /medieval_total_war/b6001/128918596/r128999946 (653 words)

	My CPU has support for SSE2, SSE3 instructions? - TalkingSoft.com Forums
		This permits mixing integer SIMD and scalar floating point operations without the time-consuming mode switching required in MMX and SSE.
		Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information.
		The additional registers are only visible when the processor is running in the 64-bit mode, known as AMD64.
	www.click-now.net /forums/index.php?showtopic=271 (453 words)

	Debian -- atlas3-sse2
		Currently ATLAS supplies optimized versions for the complete set of linear algebra kernels known as the Basic Linear Algebra Subroutines (BLAS), and a subset of the linear algebra routines in the LAPACK library.
		These libraries use the SSE2 extensions only available on Pentium IV and later processors.
		On some architectures, multiple binary packages are provided to take advantage of certain commonly available processor instruction set extensions.
	packages.debian.org /unstable/libs/atlas3-sse2 (184 words)

	Error "Adobe Production Studio needs a processor that supports the SSE2 instruction set..." when you install - Support ... (Site not responding. Last check: 2007-10-13)
		You can edit the Setup.ini file for Adobe Production Studio so it will not check for an SSE2 enabled CPU before it attempts to install.
		The SSE2 (Streaming SIMD Extensions 2) instruction set is included with Intel Pentium 4 and later processors and with AMD Athlon 64 and Opteron and later processors.
		Premiere Pro and Encore DVD have been optimized to use the SSE2 instruction set during real time previews and when working with MPEG source files.
	www.adobe.com /support/techdocs/332478.html (462 words)

	What is SSE2 Support? - Doom9's Forum
		SSE is a SIMD (Single Instruction, Multiple Data) instruction set architecture for your CPU.
		Of which, SSE2 is an improvement over SSE and SSE3 is an improvement over SSE2 with more instructions (If all this mean anything to you).
		But all technicalities aside, look here to see if your CPU is listed in there under 'CPUs supporting SSE2'.
	forum.doom9.org /showthread.php?p=840880#post840880 (531 words)

	SSE2 and SSE3 information PLEASE READ - InsanelyMac Forum (Site not responding. Last check: 2007-10-13)
		*SSE2 can run os x intel but with patches such as in coregraphics, there now are new patches that will allow rosetta to run.
		I read somewhere somebody has it running on a SSE cpu, so I'm going out to confirm that.
		flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr
	forum.insanelymac.com /index.php?showtopic=139 (813 words)

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