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| | DC-DC converter with saturable reactor reset circuit - Patent 4811187 (Site not responding. Last check: 2007-10-03) |
 | | An emitter of a transistor 10 for controlling the resetting of the saturable reactor 5 is connected to the positive output terminal 12, and a collector thereof is connected to a point between the saturable reactor 5 and the anode of the diode 6. |
 | | 3, a saturable reactor 5 is connected to a negative end of a secondary winding 22, and a path for reset current ir is formed along a transistor 10, a diode 15 and a saturable reactor 5 and back to a negative output terminal 13. |
 | | That is, voltage applied to the saturable reactor 105 by the controlling winding 153 is Vo.times.n.sub.M1 /n.sub.M2, wherein Vo is output voltage, and n.sub.M1 and n.sub.M2 are the numbers of turns of the first and second windings 152, 153, respectively. |
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