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Topic: Scalar processor

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	scalar from FOLDOC (Site not responding. Last check: 2007-10-30)
		Thus, for example, "scalar multiplication" refers to the operation of multiplying one number (one scalar) by another and is used to contrast this with "matrix multiplication" etc.
		In a parallel processor or vector processor, the "scalar processor" handles all the sequential operations - those which cannot be parallelised or vectorised.
		A string is regarded as a scalar in some languages (e.g.
	foldoc.org /?scalar (130 words)

	Vector processing apparatus providing vector and scalar processor synchronization - United States Patent 4,780,811
		The vector/scalar processor data transfer register appears to be a high speed memory to the scalar processor, and only the data transfer instruction from the floating point register and the fixed point register is aded to the scalar instruction architecture as a basic operation.
		In the vector processor, it is not guaranteed that the instructions are executed in the order of their appearance because of reversal of the order of execution of the vector instructions and the indefinite length of the operation time.
		As the scalar instruction is decoded by the decoder 2, the scalar instruction other than the post and wait instructions instructs the initiation of the scalar processing to the logic circuits in the scalar processor through a path 21 without checking the control condition for decoding the instruction, such as SCR.
	xrint.com /patents/us/4780811 (6713 words)

	Vector processor - Wikipedia, the free encyclopedia
		A vector processor, or array processor, is a CPU design that is able to run mathematical operations on multiple data elements simultaneously.
		This is in contrast to a scalar processor which handles one element at a time.
		Vector processors were common in the scientific computing area, where they formed the basis of most supercomputers through the 1980s and into the 1990s, but general increases in performance and processor design saw the near disappearance of the vector processor as a general-purpose CPU.
	en.wikipedia.org /wiki/Vector_processor (1579 words)

	Superscalar - Wikipedia, the free encyclopedia
		In a vector processor, by contrast, a single instruction operates simultaneously on multiple data items.
		The difference is analogous to the difference between scalar and vector arithmetic.
		A superscalar processor is sort of a mixture of the two.
	en.wikipedia.org /wiki/Superscalar (717 words)

	Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector ...
		Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit.
		The processor of claim 1, wherein vector instructions and scalar instructions each include a bit sequence at predetermined bit locations, said bit sequence being detectable by the instruction decoder to identify an instruction as a scalar instruction or a vector instruction.
		The scalar result unit operates on the final outputs from the pixel processing units 16 and the result may be written to one of the scalar registers r.sub.0 to r.sub.6, and the scalar flags will be set accordingly.
	www.freepatentsonline.com /7167972.html (5080 words)

	VAX MACRO and Instruction Set Reference Manual (Site not responding. Last check: 2007-10-30)
		While the vector processor is disabled, and in the absence of hardware errors, it will complete all pending instructions in its instruction queue including those sent by the scalar processor after the vector processor became disabled.
		If the new process executing on the scalar processor has a vector instruction to execute, saving and restoring the state of the vector processor---that is, vector context switching---is done as part of handling a subsequent vector processor disabled fault.
		Scalar/vector memory synchronization allows software to ensure that the memory activity of the scalar/vector processor pair has ceased and the resultant memory write operations have been made visible to each processor in the pair before the pair's scalar processor proceeds with the next instruction.
	www.cuis.edu /doc_vms_html/000000/731final/4515/4515pro_033.html (3025 words)

	The mpC Programming Language Specification
		In this case, the execution of the operator consists in sending i-th element of the vector to i-th (in the natural numeration) processor of R, where the element is assigned to i-th component of the left operand for all i from 0 to N-1.
		A statement may be executed either on a single processor, or on a region of the computing space (a network or a subnetwork), or on a set of regions, or on the entire computing space.
		The latter means that the processor executing the break statement terminates its execution of the pipe statement and sends the signal of preschedule termination to processors taking part in the execution of the pipe statement.
	www.ispras.ru /~mpc/mpc-spec.html (14619 words)

	Understanding some simple processor-performance limits
		To understand processor performance, it is essential to use metrics that are intuitive, and it is essential to be familiar with a few aspects of a simple scalar pipeline before attempting to understand more complex structures.
		That is, scalar pipeline performance (in units of CPI) can be split into three relatively independent pieces: one involving the inherent execution component of the workload (cited incorrectly as "performance" in many studies), one involving pipeline effects, and one involving the memory hierarchy.
		In particular, the FCE is identical; scalar EBusy is an upper bound; and scalar EIdle is a lower bound.
	www.research.ibm.com /journal/rd/413/emma.html (11165 words)

	[No title]
		Lecture 16 11/03/1994 Vector Processing ----------------- A vector processor consists of a scalar processor and a vector unit, which could be thought of as an independent functional unit capable of efficient vector operations.
		Scalar instructions are executed on the scalar processor, whereas vector instructions are executed on the vector unit.
		The ISA of a scalar processor is augmented with vector instructions of the following types: o Vector-vector instructions: f1: Vi --> Vj (e.g.
	www.cs.bu.edu /fac/best/crs/cs551/lectures/lecture-16.html (1151 words)

	EDN Access -- 03.01.96 Oxford Computer A236 16-bit fixed-point DSP
		You can use the scalar processor for scalar arithmetic and Boolean operations; for program control; and for computation of data addresses, program addresses, and loop counts.
		The scalar processor has a triple-port register stack with 32 registers and an ALU.
		The vector processors support the storage of 8- and 16-bit parallel data types to maximize memory utilization.
	www.edn.com /archives/1996/030196/05dsp11.htm (564 words)

	Frequently Asked Questions About the A236 Parallel Video DSP Chip (Site not responding. Last check: 2007-10-30)
		In the scalar processor, an address is generated in one cycle and a memory operation is done in the next cycle, so at least two cycles are required.
		The scalar processor generates a 24-bit address that is used to fetch an 8-byte operand from memory.
		The scalar processor generates a 24-bit address that is used to fetch an operand from memory.
	www.omdi.com /a236_faq.html (8084 words)

	OpenVMS System Manager's Manual (Site not responding. Last check: 2007-10-30)
		All processors in a multiprocessing environment must be at the same hardware and firmware level to guarantee that a given processor is capable of resuming the execution thread of a process that had been executing previously on another processor in the system.
		Vector processors gain a further speed advantage over scalar processors by their use of special hardware techniques designed for the fast processing of streams of data.
		If the image the process is executing issues only scalar instructions for a period of time, and it must share the scalar-vector processor pair with other vector consumers, its inability to run on an available scalar processor could hamper its performance and the overall performance of the system.
	www.cuis.edu /doc_vms_html/000000/731final/6017/6017pro_108.html (2704 words)

	Embedded.com - Advanced Processor Features and Why You Should Care: Part 1
		While 8-and 16-bit processors still have a place in certain applications, the industry is increasingly moving to 32-and 64-bit processors.
		Processor families such as the Intel Pentium and i80960 were early examples of super-scalar processors.
		If your processor is super-scalar and supports OOO execution, then you should at least consider the possibility that some of your bugs may induced by the hardware doing more for you than you expected.
	www.embedded.com /showArticle.jhtml?articleID=183702541 (2536 words)

	Lecture 16
		It provides a population count for compressing sparse arrays, if the bits in a scalar value are counted and summed appropriately, a global add-reduce operation can be computed more quickly than through a combining network in some cases, and it allows a histogram to be computed in time proportional to the number of buckets.
		The other alternative is to use a wide microprogrammed processor, something like a VLIW machine, but where each portion of the instruction word drives either a piece of the control unit (instruction fetch, data address calculation, issue, status check, etc.) or the array (embedded array opcodes).
		If a processor is assumed to virtualize to a minimum degree, then the communication between chips is greatly reduced because it can be orchestrated so that tiles that send data off the chip can be processed first and tiles that receive data from off the chip can be processed last.
	www.cs.umass.edu /~weems/CmpSci635/635lecture16.html (5577 words)

	Optimizing Processor-bound Code
		A scalar is a single value, including a single element of an array, that can be manipulated by a superscalar processor.
		Scalar processing consists of logical, arithmetic, or memory operations performed on operands in scalar registers, one at a time.
		Second, the vector processor chains all like operations and performs them in order, then moves on to the next set of like operations, and so on until the entire task is completed.
	docs.cray.com /books/S-2315-52/html-S-2315-52/z1073673157.html (2632 words)

	High Performance Computing and Communications Glossary
		scan-vector model (n.) A theoretical model of parallel computing in which a scalar processor and a vector processor have access, respectively to a memory holding scalar values and a memory holding vectors of arbitrary length.
		stripmining (n.) a process used by a compiler on a register-to-register vector processor whereby a DO-loop of long or variable iteration count is executed in strips which are the length of a vector register, except for a remainder strip whose length is less.
		While super-linear speedup is theoretically impossible, in practice it may occur because distributing a problem among many processors may increase the effective total size of the cache being used, or because distribution may change the order in which nondeterministic operations are carried out, which can lead to earlier termination of the program.
	wotug.ukc.ac.uk /parallel/acronyms/hpccgloss/S.html (2611 words)

	Asynchronous Heterogeneity: The Next Big Thing In HEC
		Recall that the phrase "commodity processor" typically means a single-core RISC superscalar processor optimized for single-thread performance and dependent for its performance both on its cache and on complex, power-hungry control circuitry for out-of-order execution.
		Recently, processor vendors with complex microarchitectures trying to scale to higher single-processor performance have been forced by the laws of physics to move to multicore microarchitectures (2X, 4X, 8X,...), where each core is just a smaller instance of the _same_ conventional, complex, power-hungry design.
		Heavyweight processors are responsible for executing the compute-intensive portions of an application, and combine the best aspects of multithreading, vector computing, and stream processing for very high-throughput execution of the compute-intensive portions.
	www.hpcwire.com /hpc/450881.html (4724 words)

	MVPsim
		The actual processor to be modeled is a "standard" super-scalar processor that is able to use cache-misses to switch between up to four hardware contexts.
		Each context has a valid bit to let the processor know if it is allowed to fetch instructions for the context and a ready bit to denote if the thread is ready to execute of waiting for a cache miss to return.
		When a cache miss occurs, the processor sets the H0 ready bit to 0, switches to H1, and (since H1 is not a valid context and More Threads is 1) sets H1 context valid to 1 and runs the interrupt handler in H1.
	web.engr.oregonstate.edu /~benl/Research/MVP/mvp.html (5241 words)

	scalar from FOLDOC (Site not responding. Last check: 2007-10-30)
		Thus, for example, "scalar multiplication" refers to the operation of multiplying one number (one scalar) by another and is used to contrast this with "matrix multiplication" etc.
		In a parallel processor or vector processor, the "scalar processor" handles all the sequential operations - those which cannot be parallelised or vectorised.
		A string is regarded as a scalar in some languages (e.g.
	ftp.sunet.se /foldoc/foldoc.cgi?query=scalar (130 words)

	Hip, hip, ouray!
		It has 16 times as much memory as shavano, and although its processor speed is about one-half the speed of a Y-MP processor, it sustains up to twice the gigaflops as shavano due to its increased number of processors and vastly increased memory.
		The original J90 systems (such as aztec and paiute) are now referred to as "J90 classics." The J90 classic systems clock their scalar and vector processors at 100 MHz and the theoretical peak performance is 200 megaflops per CPU.
		Though the theoretical peak performance of a J90se processor remains at 200 MHz, because of its double-speed scalar processor, the delivered performance on typical "real world" codes is improved over the J90 classic systems.
	www.cisl.ucar.edu /zine/97/fall/text/2.ouray.html (521 words)

	[No title]
		Scalar operations are non-vector operations composed of constructs, which perform flow control or, decision-making construct operations.
		Considering that vector math operations typically account for the majority of the DSP processing in many applications, a simplified solution is requiredpresented which meetstakes advantage of the performance and flexibility of both approaches while meeting the size, weight, power constraints requirements of the space community.
		The A VP is a “pass-based” processor where a single instruction from the algorithm PROM is implemented as a DSP function on the entire vector array that is passed through the chip from one port to another.
	klabs.org /richcontent/MAPLDCon99/Papers/P16_PRADO_P.doc (3046 words)

	Programming high-performance applications on the Cell BE processor, Part 5: Programming the SPU in C/C++
		In Part 5 of the Programming high-performance applications on the Cell BE processor series, apply your knowledge of the synergistic processing unit (SPU) to programming the Cell Broadband Engine™ (Cell BE) processor in C/C++.
		The primary difference between vector processors and non-vector processors is that vector processors have large registers which allow them to store multiple values (called elements) of the same data type and process them with the same operation at once.
		On vector processors a register is treated both as a single unit and as multiple units.
	www-128.ibm.com /developerworks/power/library/pa-linuxps3-5 (3910 words)

	Success Stories
		With the AMD Opteron™ processor and Egenera® BladeFrame™ system we reduced floor space by 60 percent and dramatically improved efficiency while increasing capacity three-fold.
		The AMD Opteron processor gave us a 20 to 40 percent increase in performance compared to other processors.
		And the AMD Athlon processors are very well supported by the operating systems that we run on them.
	www.amd.com /us-en/Corporate/VirtualPressRoom/0,,51_104_566,00.html (3821 words)

	Windows Vista Benchmark: 64-Bit Faster Than 32-Bit
		Basically an x64 processor is new type of processor with 64-bit extensions.
		So, if you are using a 32-bit operating system on an x64 processor, you are not fully utilizing it.
		64-bit long mode has several advantages: it allows the processor to break the 4gb memory barrier and also 64-bit long mode enables twice the number of general purpose registers than in 32-bit mode… which explains why it is faster than a 32-bit processor/mode.
	64-bit-computers.com /windows-vista-32-bit-vs-64-bit-benchmark.html (1245 words)

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