| | Shift-Register Stream Ciphers |
 | | In addition to the conventional configuration, where each new bit input to the shift register is the XOR of several bits in the register, a shift register may also be implemented in Galois configuration, where the single bit shifted out of the register is XORed with several bits in the shift register. |
 | | Doing that is exactly equivalent to running the shift register in the Galois configuration, and so the reason for the condition is now obvious: if the shift register has maximum period, the 0000001 state will recur at the end of that period; and if it does so recur, this recurrence mustn't be a repeated occurrence. |
 | | If only four shift registers are used, so that we XOR the output of one shift register with the output of a Geffe generator, then we still have the same weakness that the Geffe generator alone had. |
| www.quadibloc.com /crypto/co040801.htm (2247 words) |